PPCISelLowering.h revision 3d90dbee695e723f422dafca3fc75f193268ab9e
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "PPC.h" 21#include "PPCSubtarget.h" 22 23namespace llvm { 24 namespace PPCISD { 25 enum NodeType { 26 // Start the numbering where the builtin ops and target ops leave off. 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 29 /// FSEL - Traditional three-operand fsel node. 30 /// 31 FSEL, 32 33 /// FCFID - The FCFID instruction, taking an f64 operand and producing 34 /// and f64 value containing the FP representation of the integer that 35 /// was temporarily in the f64 operand. 36 FCFID, 37 38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 39 /// operand, producing an f64 value containing the integer representation 40 /// of that FP value. 41 FCTIDZ, FCTIWZ, 42 43 /// STFIWX - The STFIWX instruction. The first operand is an input token 44 /// chain, then an f64 value to store, then an address to store it to. 45 STFIWX, 46 47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 48 // three v4f32 operands and producing a v4f32 result. 49 VMADDFP, VNMSUBFP, 50 51 /// VPERM - The PPC VPERM Instruction. 52 /// 53 VPERM, 54 55 /// Hi/Lo - These represent the high and low 16-bit parts of a global 56 /// address respectively. These nodes have two operands, the first of 57 /// which must be a TargetGlobalAddress, and the second of which must be a 58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 59 /// though these are usually folded into other nodes. 60 Hi, Lo, 61 62 TOC_ENTRY, 63 64 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 65 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 66 /// compute an allocation on the stack. 67 DYNALLOC, 68 69 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 70 /// at function entry, used for PIC code. 71 GlobalBaseReg, 72 73 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 74 /// shift amounts. These nodes are generated by the multi-precision shift 75 /// code. 76 SRL, SRA, SHL, 77 78 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 79 /// registers. 80 EXTSW_32, 81 82 /// CALL - A direct function call. 83 CALL_Darwin, CALL_SVR4, 84 85 /// NOP - Special NOP which follows 64-bit SVR4 calls. 86 NOP, 87 88 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 89 /// MTCTR instruction. 90 MTCTR, 91 92 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 93 /// BCTRL instruction. 94 BCTRL_Darwin, BCTRL_SVR4, 95 96 /// Return with a flag operand, matched by 'blr' 97 RET_FLAG, 98 99 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. 100 /// This copies the bits corresponding to the specified CRREG into the 101 /// resultant GPR. Bits corresponding to other CR regs are undefined. 102 MFCR, 103 104 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 105 /// instructions. For lack of better number, we use the opcode number 106 /// encoding for the OPC field to identify the compare. For example, 838 107 /// is VCMPGTSH. 108 VCMP, 109 110 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 111 /// altivec VCMP*o instructions. For lack of better number, we use the 112 /// opcode number encoding for the OPC field to identify the compare. For 113 /// example, 838 is VCMPGTSH. 114 VCMPo, 115 116 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 117 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 118 /// condition register to branch on, OPC is the branch opcode to use (e.g. 119 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 120 /// an optional input flag argument. 121 COND_BRANCH, 122 123 // The following 5 instructions are used only as part of the 124 // long double-to-int conversion sequence. 125 126 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the 127 /// register. 128 MFFS, 129 130 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR. 131 MTFSB0, 132 133 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR. 134 MTFSB1, 135 136 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with 137 /// rounding towards zero. It has flags added so it won't move past the 138 /// FPSCR-setting instructions. 139 FADDRTZ, 140 141 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. 142 MTFSF, 143 144 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 145 /// reserve indexed. This is used to implement atomic operations. 146 LARX, 147 148 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 149 /// indexed. This is used to implement atomic operations. 150 STCX, 151 152 /// TC_RETURN - A tail call return. 153 /// operand #0 chain 154 /// operand #1 callee (register or absolute) 155 /// operand #2 stack adjustment 156 /// operand #3 optional in flag 157 TC_RETURN, 158 159 /// STD_32 - This is the STD instruction for use with "32-bit" registers. 160 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE, 161 162 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 163 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 164 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 165 /// i32. 166 STBRX, 167 168 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 169 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 170 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 171 /// or i32. 172 LBRX 173 }; 174 } 175 176 /// Define some predicates that are used for node matching. 177 namespace PPC { 178 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 179 /// VPKUHUM instruction. 180 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 181 182 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 183 /// VPKUWUM instruction. 184 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 185 186 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 187 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 188 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 189 bool isUnary); 190 191 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 192 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 193 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 194 bool isUnary); 195 196 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 197 /// amount, otherwise return -1. 198 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 199 200 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 201 /// specifies a splat of a single element that is suitable for input to 202 /// VSPLTB/VSPLTH/VSPLTW. 203 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 204 205 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 206 /// are -0.0. 207 bool isAllNegativeZeroVector(SDNode *N); 208 209 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 210 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 211 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 212 213 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 214 /// formed by using a vspltis[bhw] instruction of the specified element 215 /// size, return the constant being splatted. The ByteSize field indicates 216 /// the number of bytes of each element [124] -> [bhw]. 217 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 218 } 219 220 class PPCTargetLowering : public TargetLowering { 221 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 222 int VarArgsStackOffset; // StackOffset for start of stack 223 // arguments. 224 unsigned VarArgsNumGPR; // Index of the first unused integer 225 // register for parameter passing. 226 unsigned VarArgsNumFPR; // Index of the first unused double 227 // register for parameter passing. 228 const PPCSubtarget &PPCSubTarget; 229 public: 230 explicit PPCTargetLowering(PPCTargetMachine &TM); 231 232 /// getTargetNodeName() - This method returns the name of a target specific 233 /// DAG node. 234 virtual const char *getTargetNodeName(unsigned Opcode) const; 235 236 /// getSetCCResultType - Return the ISD::SETCC ValueType 237 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 238 239 /// getPreIndexedAddressParts - returns true by value, base pointer and 240 /// offset pointer and addressing mode by reference if the node's address 241 /// can be legally represented as pre-indexed load / store address. 242 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 243 SDValue &Offset, 244 ISD::MemIndexedMode &AM, 245 SelectionDAG &DAG) const; 246 247 /// SelectAddressRegReg - Given the specified addressed, check to see if it 248 /// can be represented as an indexed [r+r] operation. Returns false if it 249 /// can be more efficiently represented with [r+imm]. 250 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 251 SelectionDAG &DAG) const; 252 253 /// SelectAddressRegImm - Returns true if the address N can be represented 254 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 255 /// is not better represented as reg+reg. 256 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 257 SelectionDAG &DAG) const; 258 259 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 260 /// represented as an indexed [r+r] operation. 261 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 262 SelectionDAG &DAG) const; 263 264 /// SelectAddressRegImmShift - Returns true if the address N can be 265 /// represented by a base register plus a signed 14-bit displacement 266 /// [r+imm*4]. Suitable for use by STD and friends. 267 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, 268 SelectionDAG &DAG) const; 269 270 271 /// LowerOperation - Provide custom lowering hooks for some operations. 272 /// 273 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 274 275 /// ReplaceNodeResults - Replace the results of node with an illegal result 276 /// type with new values built out of custom code. 277 /// 278 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 279 SelectionDAG &DAG); 280 281 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 282 283 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 284 const APInt &Mask, 285 APInt &KnownZero, 286 APInt &KnownOne, 287 const SelectionDAG &DAG, 288 unsigned Depth = 0) const; 289 290 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 291 MachineBasicBlock *MBB, 292 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 293 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 294 MachineBasicBlock *MBB, bool is64Bit, 295 unsigned BinOpcode) const; 296 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 297 MachineBasicBlock *MBB, 298 bool is8bit, unsigned Opcode) const; 299 300 ConstraintType getConstraintType(const std::string &Constraint) const; 301 std::pair<unsigned, const TargetRegisterClass*> 302 getRegForInlineAsmConstraint(const std::string &Constraint, 303 EVT VT) const; 304 305 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 306 /// function arguments in the caller parameter area. This is the actual 307 /// alignment, not its logarithm. 308 unsigned getByValTypeAlignment(const Type *Ty) const; 309 310 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 311 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 312 /// true it means one of the asm constraint of the inline asm instruction 313 /// being processed is 'm'. 314 virtual void LowerAsmOperandForConstraint(SDValue Op, 315 char ConstraintLetter, 316 bool hasMemory, 317 std::vector<SDValue> &Ops, 318 SelectionDAG &DAG) const; 319 320 /// isLegalAddressingMode - Return true if the addressing mode represented 321 /// by AM is legal for this target, for a load/store of the specified type. 322 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 323 324 /// isLegalAddressImmediate - Return true if the integer value can be used 325 /// as the offset of the target addressing mode for load / store of the 326 /// given type. 327 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; 328 329 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 330 /// the offset of the target addressing mode. 331 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 332 333 virtual bool 334 IsEligibleForTailCallOptimization(SDValue Callee, 335 CallingConv::ID CalleeCC, 336 bool isVarArg, 337 const SmallVectorImpl<ISD::InputArg> &Ins, 338 SelectionDAG& DAG) const; 339 340 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 341 342 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 343 bool isSrcConst, bool isSrcStr, 344 SelectionDAG &DAG) const; 345 346 /// getFunctionAlignment - Return the Log2 alignment of this function. 347 virtual unsigned getFunctionAlignment(const Function *F) const; 348 349 private: 350 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 351 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 352 353 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 354 int SPDiff, 355 SDValue Chain, 356 SDValue &LROpOut, 357 SDValue &FPOpOut, 358 bool isDarwinABI, 359 DebugLoc dl); 360 361 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 362 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 363 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 364 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 365 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 366 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 367 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 368 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 369 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 370 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 371 int VarArgsFrameIndex, int VarArgsStackOffset, 372 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, 373 const PPCSubtarget &Subtarget); 374 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex, 375 int VarArgsStackOffset, unsigned VarArgsNumGPR, 376 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget); 377 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 378 const PPCSubtarget &Subtarget); 379 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 380 const PPCSubtarget &Subtarget); 381 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); 382 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl); 383 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 384 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 385 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG); 386 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG); 387 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG); 388 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 389 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 390 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 391 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 392 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG); 393 394 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 395 CallingConv::ID CallConv, bool isVarArg, 396 const SmallVectorImpl<ISD::InputArg> &Ins, 397 DebugLoc dl, SelectionDAG &DAG, 398 SmallVectorImpl<SDValue> &InVals); 399 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, 400 bool isVarArg, 401 SelectionDAG &DAG, 402 SmallVector<std::pair<unsigned, SDValue>, 8> 403 &RegsToPass, 404 SDValue InFlag, SDValue Chain, 405 SDValue &Callee, 406 int SPDiff, unsigned NumBytes, 407 const SmallVectorImpl<ISD::InputArg> &Ins, 408 SmallVectorImpl<SDValue> &InVals); 409 410 virtual SDValue 411 LowerFormalArguments(SDValue Chain, 412 CallingConv::ID CallConv, bool isVarArg, 413 const SmallVectorImpl<ISD::InputArg> &Ins, 414 DebugLoc dl, SelectionDAG &DAG, 415 SmallVectorImpl<SDValue> &InVals); 416 417 virtual SDValue 418 LowerCall(SDValue Chain, SDValue Callee, 419 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 420 const SmallVectorImpl<ISD::OutputArg> &Outs, 421 const SmallVectorImpl<ISD::InputArg> &Ins, 422 DebugLoc dl, SelectionDAG &DAG, 423 SmallVectorImpl<SDValue> &InVals); 424 425 virtual SDValue 426 LowerReturn(SDValue Chain, 427 CallingConv::ID CallConv, bool isVarArg, 428 const SmallVectorImpl<ISD::OutputArg> &Outs, 429 DebugLoc dl, SelectionDAG &DAG); 430 431 SDValue 432 LowerFormalArguments_Darwin(SDValue Chain, 433 CallingConv::ID CallConv, bool isVarArg, 434 const SmallVectorImpl<ISD::InputArg> &Ins, 435 DebugLoc dl, SelectionDAG &DAG, 436 SmallVectorImpl<SDValue> &InVals); 437 SDValue 438 LowerFormalArguments_SVR4(SDValue Chain, 439 CallingConv::ID CallConv, bool isVarArg, 440 const SmallVectorImpl<ISD::InputArg> &Ins, 441 DebugLoc dl, SelectionDAG &DAG, 442 SmallVectorImpl<SDValue> &InVals); 443 444 SDValue 445 LowerCall_Darwin(SDValue Chain, SDValue Callee, 446 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 447 const SmallVectorImpl<ISD::OutputArg> &Outs, 448 const SmallVectorImpl<ISD::InputArg> &Ins, 449 DebugLoc dl, SelectionDAG &DAG, 450 SmallVectorImpl<SDValue> &InVals); 451 SDValue 452 LowerCall_SVR4(SDValue Chain, SDValue Callee, 453 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 454 const SmallVectorImpl<ISD::OutputArg> &Outs, 455 const SmallVectorImpl<ISD::InputArg> &Ins, 456 DebugLoc dl, SelectionDAG &DAG, 457 SmallVectorImpl<SDValue> &InVals); 458 }; 459} 460 461#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 462