PPCISelLowering.h revision 44ab89eb376af838d1123293a79975aede501464
1fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 3a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// The LLVM Compiler Infrastructure 4a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 5a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// This file is distributed under the University of Illinois Open Source 6a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// License. See LICENSE.TXT for details. 7a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 8fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard//===----------------------------------------------------------------------===// 9a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 10fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard// This file defines the interfaces that PPC uses to lower LLVM code into a 11fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard// selection DAG. 12fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard// 13a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 14fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard 15a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 18a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "llvm/Target/TargetLowering.h" 19b655f78b25454e00f4300fb5ccd35b3d0ab8a740Vadim Girlin#include "llvm/CodeGen/SelectionDAG.h" 20788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard#include "PPC.h" 21a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "PPCSubtarget.h" 22a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 23a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardnamespace llvm { 24a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard namespace PPCISD { 25a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard enum NodeType { 26a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard // Start the numbering where the builtin ops and target ops leave off. 27a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard FIRST_NUMBER = ISD::BUILTIN_OP_END, 2876b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard 29a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// FSEL - Traditional three-operand fsel node. 30a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// 31a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard FSEL, 3276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard 33a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// FCFID - The FCFID instruction, taking an f64 operand and producing 34a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// and f64 value containing the FP representation of the integer that 35a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// was temporarily in the f64 operand. 36a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard FCFID, 37a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 38a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 39a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// operand, producing an f64 value containing the integer representation 40a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// of that FP value. 41a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard FCTIDZ, FCTIWZ, 42a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 43a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// STFIWX - The STFIWX instruction. The first operand is an input token 44a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// chain, then an f64 value to store, then an address to store it to. 45a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard STFIWX, 46a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 47a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 48a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard // three v4f32 operands and producing a v4f32 result. 49a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard VMADDFP, VNMSUBFP, 50a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 51a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// VPERM - The PPC VPERM Instruction. 52a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// 53a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard VPERM, 54a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 55a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// Hi/Lo - These represent the high and low 16-bit parts of a global 56a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// address respectively. These nodes have two operands, the first of 57a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// which must be a TargetGlobalAddress, and the second of which must be a 58a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 59a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// though these are usually folded into other nodes. 60a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard Hi, Lo, 61a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 62a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard TOC_ENTRY, 63a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 64a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// The following three target-specific nodes are used for calls through 65a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// function pointers in the 64-bit SVR4 ABI. 66a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 67a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// Restore the TOC from the TOC save area of the current stack frame. 68a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// This is basically a hard coded load instruction which additionally 69a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// takes/produces a flag. 70a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard TOC_RESTORE, 71a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 728263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune /// Like a regular LOAD but additionally taking/producing a flag. 738263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune LOAD, 748263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune 758263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is 76a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// a hard coded load instruction. 7776b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard LOAD_TOC, 78a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 79a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 8076b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 81a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// compute an allocation on the stack. 82a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard DYNALLOC, 8376b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard 84a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 85a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// at function entry, used for PIC code. 8676b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard GlobalBaseReg, 87a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 88a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 89a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// shift amounts. These nodes are generated by the multi-precision shift 90a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// code. 918263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune SRL, SRA, SHL, 928263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune 938263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 948263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune /// registers. 958263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune EXTSW_32, 968263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune 9776b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard /// CALL - A direct function call. 98a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard CALL_Darwin, CALL_SVR4, 99a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 100a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// NOP - Special NOP which follows 64-bit SVR4 calls. 101b3863eb9a5a7a844f04acde5f15151c898ff3bacTom Stellard NOP, 102a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 103a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 104a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// MTCTR instruction. 105a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MTCTR, 106a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 107a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 108a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// BCTRL instruction. 109a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard BCTRL_Darwin, BCTRL_SVR4, 110a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 111a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// Return with a flag operand, matched by 'blr' 112a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard RET_FLAG, 113a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 114a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF 115a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// instructions. This copies the bits corresponding to the specified 116a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// CRREG into the resultant GPR. Bits corresponding to other CR regs 117a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// are undefined. 118a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MFCR, 119a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 120a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 121a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// instructions. For lack of better number, we use the opcode number 122a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// encoding for the OPC field to identify the compare. For example, 838 123a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// is VCMPGTSH. 124a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard VCMP, 125a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 126a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 127a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// altivec VCMP*o instructions. For lack of better number, we use the 128a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// opcode number encoding for the OPC field to identify the compare. For 129a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// example, 838 is VCMPGTSH. 130a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard VCMPo, 131a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 132a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 133a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 134a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// condition register to branch on, OPC is the branch opcode to use (e.g. 13576b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 136a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// an optional input flag argument. 137a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard COND_BRANCH, 138a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 139a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard // The following 5 instructions are used only as part of the 140a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard // long double-to-int conversion sequence. 141a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 142a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the 143a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// register. 144a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MFFS, 145a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 146a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR. 147a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MTFSB0, 148a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 149a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR. 150a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MTFSB1, 151a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 15276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with 153a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// rounding towards zero. It has flags added so it won't move past the 154a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// FPSCR-setting instructions. 155a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard FADDRTZ, 156a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 157a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. 158a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MTFSF, 159a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 160a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 161a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// reserve indexed. This is used to implement atomic operations. 162a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard LARX, 163a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 164a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// STCX = This corresponds to PPC stcx. instrcution: store conditional 165a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// indexed. This is used to implement atomic operations. 166a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard STCX, 167a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 168a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// TC_RETURN - A tail call return. 169a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// operand #0 chain 170a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// operand #1 callee (register or absolute) 171a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// operand #2 stack adjustment 172a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// operand #3 optional in flag 173a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard TC_RETURN, 174a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 175a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// STD_32 - This is the STD instruction for use with "32-bit" registers. 176a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE, 177a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 178a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 179a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 180a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// the GPRC input, then stores it through Ptr. Type can be either i16 or 181a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// i32. 182a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard STBRX, 183a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 184a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 185a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 186788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 187788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// or i32. 188788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard LBRX 189788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard }; 190788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard } 191788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard 192788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// Define some predicates that are used for node matching. 193788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard namespace PPC { 194788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 195788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// VPKUHUM instruction. 196788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 197788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard 198788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 199788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// VPKUWUM instruction. 200788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 201788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard 202788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 203788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 204788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 205788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard bool isUnary); 206788fd04dacb9eb1e32010050c57cd2f49779311bTom Stellard 207 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 208 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 209 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 210 bool isUnary); 211 212 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 213 /// amount, otherwise return -1. 214 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 215 216 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 217 /// specifies a splat of a single element that is suitable for input to 218 /// VSPLTB/VSPLTH/VSPLTW. 219 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 220 221 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 222 /// are -0.0. 223 bool isAllNegativeZeroVector(SDNode *N); 224 225 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 226 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 227 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 228 229 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 230 /// formed by using a vspltis[bhw] instruction of the specified element 231 /// size, return the constant being splatted. The ByteSize field indicates 232 /// the number of bytes of each element [124] -> [bhw]. 233 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 234 } 235 236 class PPCTargetLowering : public TargetLowering { 237 const PPCSubtarget &PPCSubTarget; 238 239 public: 240 explicit PPCTargetLowering(PPCTargetMachine &TM); 241 242 /// getTargetNodeName() - This method returns the name of a target specific 243 /// DAG node. 244 virtual const char *getTargetNodeName(unsigned Opcode) const; 245 246 /// getSetCCResultType - Return the ISD::SETCC ValueType 247 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 248 249 /// getPreIndexedAddressParts - returns true by value, base pointer and 250 /// offset pointer and addressing mode by reference if the node's address 251 /// can be legally represented as pre-indexed load / store address. 252 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 253 SDValue &Offset, 254 ISD::MemIndexedMode &AM, 255 SelectionDAG &DAG) const; 256 257 /// SelectAddressRegReg - Given the specified addressed, check to see if it 258 /// can be represented as an indexed [r+r] operation. Returns false if it 259 /// can be more efficiently represented with [r+imm]. 260 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 261 SelectionDAG &DAG) const; 262 263 /// SelectAddressRegImm - Returns true if the address N can be represented 264 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 265 /// is not better represented as reg+reg. 266 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 267 SelectionDAG &DAG) const; 268 269 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 270 /// represented as an indexed [r+r] operation. 271 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 272 SelectionDAG &DAG) const; 273 274 /// SelectAddressRegImmShift - Returns true if the address N can be 275 /// represented by a base register plus a signed 14-bit displacement 276 /// [r+imm*4]. Suitable for use by STD and friends. 277 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, 278 SelectionDAG &DAG) const; 279 280 281 /// LowerOperation - Provide custom lowering hooks for some operations. 282 /// 283 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 284 285 /// ReplaceNodeResults - Replace the results of node with an illegal result 286 /// type with new values built out of custom code. 287 /// 288 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 289 SelectionDAG &DAG) const; 290 291 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 292 293 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 294 const APInt &Mask, 295 APInt &KnownZero, 296 APInt &KnownOne, 297 const SelectionDAG &DAG, 298 unsigned Depth = 0) const; 299 300 virtual MachineBasicBlock * 301 EmitInstrWithCustomInserter(MachineInstr *MI, 302 MachineBasicBlock *MBB) const; 303 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 304 MachineBasicBlock *MBB, bool is64Bit, 305 unsigned BinOpcode) const; 306 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 307 MachineBasicBlock *MBB, 308 bool is8bit, unsigned Opcode) const; 309 310 ConstraintType getConstraintType(const std::string &Constraint) const; 311 312 /// Examine constraint string and operand type and determine a weight value. 313 /// The operand object must already have been set up with the operand type. 314 ConstraintWeight getSingleConstraintMatchWeight( 315 AsmOperandInfo &info, const char *constraint) const; 316 317 std::pair<unsigned, const TargetRegisterClass*> 318 getRegForInlineAsmConstraint(const std::string &Constraint, 319 EVT VT) const; 320 321 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 322 /// function arguments in the caller parameter area. This is the actual 323 /// alignment, not its logarithm. 324 unsigned getByValTypeAlignment(const Type *Ty) const; 325 326 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 327 /// vector. If it is invalid, don't add anything to Ops. 328 virtual void LowerAsmOperandForConstraint(SDValue Op, 329 char ConstraintLetter, 330 std::vector<SDValue> &Ops, 331 SelectionDAG &DAG) const; 332 333 /// isLegalAddressingMode - Return true if the addressing mode represented 334 /// by AM is legal for this target, for a load/store of the specified type. 335 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 336 337 /// isLegalAddressImmediate - Return true if the integer value can be used 338 /// as the offset of the target addressing mode for load / store of the 339 /// given type. 340 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; 341 342 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 343 /// the offset of the target addressing mode. 344 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 345 346 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 347 348 /// getOptimalMemOpType - Returns the target specific optimal type for load 349 /// and store operations as a result of memset, memcpy, and memmove 350 /// lowering. If DstAlign is zero that means it's safe to destination 351 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 352 /// means there isn't a need to check it against alignment requirement, 353 /// probably because the source does not need to be loaded. If 354 /// 'NonScalarIntSafe' is true, that means it's safe to return a 355 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 356 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 357 /// constant so it does not need to be loaded. 358 /// It returns EVT::Other if the type should be determined using generic 359 /// target-independent logic. 360 virtual EVT 361 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 362 bool NonScalarIntSafe, bool MemcpyStrSrc, 363 MachineFunction &MF) const; 364 365 /// getFunctionAlignment - Return the Log2 alignment of this function. 366 virtual unsigned getFunctionAlignment(const Function *F) const; 367 368 private: 369 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 370 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 371 372 bool 373 IsEligibleForTailCallOptimization(SDValue Callee, 374 CallingConv::ID CalleeCC, 375 bool isVarArg, 376 const SmallVectorImpl<ISD::InputArg> &Ins, 377 SelectionDAG& DAG) const; 378 379 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 380 int SPDiff, 381 SDValue Chain, 382 SDValue &LROpOut, 383 SDValue &FPOpOut, 384 bool isDarwinABI, 385 DebugLoc dl) const; 386 387 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 388 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 389 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 390 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 391 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 392 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 393 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 394 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 395 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 396 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 397 const PPCSubtarget &Subtarget) const; 398 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 399 const PPCSubtarget &Subtarget) const; 400 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 401 const PPCSubtarget &Subtarget) const; 402 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 403 const PPCSubtarget &Subtarget) const; 404 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 405 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const; 406 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 407 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 408 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 409 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 410 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 411 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 412 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 413 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 414 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 415 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 416 417 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 418 CallingConv::ID CallConv, bool isVarArg, 419 const SmallVectorImpl<ISD::InputArg> &Ins, 420 DebugLoc dl, SelectionDAG &DAG, 421 SmallVectorImpl<SDValue> &InVals) const; 422 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, 423 bool isVarArg, 424 SelectionDAG &DAG, 425 SmallVector<std::pair<unsigned, SDValue>, 8> 426 &RegsToPass, 427 SDValue InFlag, SDValue Chain, 428 SDValue &Callee, 429 int SPDiff, unsigned NumBytes, 430 const SmallVectorImpl<ISD::InputArg> &Ins, 431 SmallVectorImpl<SDValue> &InVals) const; 432 433 virtual SDValue 434 LowerFormalArguments(SDValue Chain, 435 CallingConv::ID CallConv, bool isVarArg, 436 const SmallVectorImpl<ISD::InputArg> &Ins, 437 DebugLoc dl, SelectionDAG &DAG, 438 SmallVectorImpl<SDValue> &InVals) const; 439 440 virtual SDValue 441 LowerCall(SDValue Chain, SDValue Callee, 442 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 443 const SmallVectorImpl<ISD::OutputArg> &Outs, 444 const SmallVectorImpl<SDValue> &OutVals, 445 const SmallVectorImpl<ISD::InputArg> &Ins, 446 DebugLoc dl, SelectionDAG &DAG, 447 SmallVectorImpl<SDValue> &InVals) const; 448 449 virtual SDValue 450 LowerReturn(SDValue Chain, 451 CallingConv::ID CallConv, bool isVarArg, 452 const SmallVectorImpl<ISD::OutputArg> &Outs, 453 const SmallVectorImpl<SDValue> &OutVals, 454 DebugLoc dl, SelectionDAG &DAG) const; 455 456 SDValue 457 LowerFormalArguments_Darwin(SDValue Chain, 458 CallingConv::ID CallConv, bool isVarArg, 459 const SmallVectorImpl<ISD::InputArg> &Ins, 460 DebugLoc dl, SelectionDAG &DAG, 461 SmallVectorImpl<SDValue> &InVals) const; 462 SDValue 463 LowerFormalArguments_SVR4(SDValue Chain, 464 CallingConv::ID CallConv, bool isVarArg, 465 const SmallVectorImpl<ISD::InputArg> &Ins, 466 DebugLoc dl, SelectionDAG &DAG, 467 SmallVectorImpl<SDValue> &InVals) const; 468 469 SDValue 470 LowerCall_Darwin(SDValue Chain, SDValue Callee, 471 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 472 const SmallVectorImpl<ISD::OutputArg> &Outs, 473 const SmallVectorImpl<SDValue> &OutVals, 474 const SmallVectorImpl<ISD::InputArg> &Ins, 475 DebugLoc dl, SelectionDAG &DAG, 476 SmallVectorImpl<SDValue> &InVals) const; 477 SDValue 478 LowerCall_SVR4(SDValue Chain, SDValue Callee, 479 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 480 const SmallVectorImpl<ISD::OutputArg> &Outs, 481 const SmallVectorImpl<SDValue> &OutVals, 482 const SmallVectorImpl<ISD::InputArg> &Ins, 483 DebugLoc dl, SelectionDAG &DAG, 484 SmallVectorImpl<SDValue> &InVals) const; 485 }; 486} 487 488#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 489