PPCISelLowering.h revision 9c61dcf1aaf275a1733b6785c54d34eda5426ae1 
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that PPC uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "PPC.h"
21
22namespace llvm {
23  namespace PPCISD {
24    enum NodeType {
25      // Start the numbering where the builting ops and target ops leave off.
26      FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
27
28      /// FSEL - Traditional three-operand fsel node.
29      ///
30      FSEL,
31
32      /// FCFID - The FCFID instruction, taking an f64 operand and producing
33      /// and f64 value containing the FP representation of the integer that
34      /// was temporarily in the f64 operand.
35      FCFID,
36
37      /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
38      /// operand, producing an f64 value containing the integer representation
39      /// of that FP value.
40      FCTIDZ, FCTIWZ,
41
42      /// STFIWX - The STFIWX instruction.  The first operand is an input token
43      /// chain, then an f64 value to store, then an address to store it to,
44      /// then a SRCVALUE for the address.
45      STFIWX,
46
47      // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48      // three v4f32 operands and producing a v4f32 result.
49      VMADDFP, VNMSUBFP,
50
51      /// LVE_X - The PPC LVE*X instructions.  The size of the element loaded is
52      /// the size of the element type of the vector result.  The element loaded
53      /// depends on the alignment of the input pointer.
54      ///
55      /// The first operand is a token chain, the second is the address to load
56      /// the third is the SRCVALUE node.
57      LVE_X,
58
59      /// VPERM - The PPC VPERM Instruction.
60      ///
61      VPERM,
62
63      /// Hi/Lo - These represent the high and low 16-bit parts of a global
64      /// address respectively.  These nodes have two operands, the first of
65      /// which must be a TargetGlobalAddress, and the second of which must be a
66      /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
67      /// though these are usually folded into other nodes.
68      Hi, Lo,
69
70      /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
71      /// at function entry, used for PIC code.
72      GlobalBaseReg,
73
74      /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
75      /// shift amounts.  These nodes are generated by the multi-precision shift
76      /// code.
77      SRL, SRA, SHL,
78
79      /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
80      /// registers.
81      EXTSW_32,
82
83      /// STD_32 - This is the STD instruction for use with "32-bit" registers.
84      STD_32,
85
86      /// CALL - A function call.
87      CALL,
88
89      /// Return with a flag operand, matched by 'blr'
90      RET_FLAG,
91    };
92  }
93
94  /// Define some predicates that are used for node matching.
95  namespace PPC {
96    /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
97    /// specifies a splat of a single element that is suitable for input to
98    /// VSPLTB/VSPLTH/VSPLTW.
99    bool isSplatShuffleMask(SDNode *N);
100
101    /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
102    /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
103    unsigned getVSPLTImmediate(SDNode *N);
104
105    /// isZeroVector - Return true if this build_vector is an all-zero vector.
106    ///
107    bool isZeroVector(SDNode *N);
108
109    /// isVecSplatImm - Return true if this is a build_vector of constants which
110    /// can be formed by using a vspltis[bhw] instruction.  The ByteSize field
111    /// indicates the number of bytes of each element [124] -> [bhw].
112    bool isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val = 0);
113  }
114
115  class PPCTargetLowering : public TargetLowering {
116    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
117    int ReturnAddrIndex;              // FrameIndex for return slot.
118  public:
119    PPCTargetLowering(TargetMachine &TM);
120
121    /// getTargetNodeName() - This method returns the name of a target specific
122    /// DAG node.
123    virtual const char *getTargetNodeName(unsigned Opcode) const;
124
125    /// LowerOperation - Provide custom lowering hooks for some operations.
126    ///
127    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
128
129    virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
130
131    /// LowerArguments - This hook must be implemented to indicate how we should
132    /// lower the arguments for the specified function, into the specified DAG.
133    virtual std::vector<SDOperand>
134      LowerArguments(Function &F, SelectionDAG &DAG);
135
136    /// LowerCallTo - This hook lowers an abstract call to a function into an
137    /// actual call.
138    virtual std::pair<SDOperand, SDOperand>
139      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
140                  unsigned CC,
141                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
142                  SelectionDAG &DAG);
143
144    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
145                                                       MachineBasicBlock *MBB);
146
147    ConstraintType getConstraintType(char ConstraintLetter) const;
148    std::vector<unsigned>
149      getRegClassForInlineAsmConstraint(const std::string &Constraint,
150                                        MVT::ValueType VT) const;
151    bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
152
153    /// isLegalAddressImmediate - Return true if the integer value can be used
154    /// as the offset of the target addressing mode.
155    virtual bool isLegalAddressImmediate(int64_t V) const;
156  };
157}
158
159#endif   // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
160