PPCISelLowering.h revision b34c79e4bbe5accbb54d0291e8bef5d2bfef32e4
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "PPC.h" 19#include "PPCSubtarget.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/Target/TargetLowering.h" 22 23namespace llvm { 24 namespace PPCISD { 25 enum NodeType { 26 // Start the numbering where the builtin ops and target ops leave off. 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 29 /// FSEL - Traditional three-operand fsel node. 30 /// 31 FSEL, 32 33 /// FCFID - The FCFID instruction, taking an f64 operand and producing 34 /// and f64 value containing the FP representation of the integer that 35 /// was temporarily in the f64 operand. 36 FCFID, 37 38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 39 /// operand, producing an f64 value containing the integer representation 40 /// of that FP value. 41 FCTIDZ, FCTIWZ, 42 43 /// STFIWX - The STFIWX instruction. The first operand is an input token 44 /// chain, then an f64 value to store, then an address to store it to. 45 STFIWX, 46 47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 48 // three v4f32 operands and producing a v4f32 result. 49 VMADDFP, VNMSUBFP, 50 51 /// VPERM - The PPC VPERM Instruction. 52 /// 53 VPERM, 54 55 /// Hi/Lo - These represent the high and low 16-bit parts of a global 56 /// address respectively. These nodes have two operands, the first of 57 /// which must be a TargetGlobalAddress, and the second of which must be a 58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 59 /// though these are usually folded into other nodes. 60 Hi, Lo, 61 62 TOC_ENTRY, 63 64 /// The following three target-specific nodes are used for calls through 65 /// function pointers in the 64-bit SVR4 ABI. 66 67 /// Restore the TOC from the TOC save area of the current stack frame. 68 /// This is basically a hard coded load instruction which additionally 69 /// takes/produces a flag. 70 TOC_RESTORE, 71 72 /// Like a regular LOAD but additionally taking/producing a flag. 73 LOAD, 74 75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is 76 /// a hard coded load instruction. 77 LOAD_TOC, 78 79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 81 /// compute an allocation on the stack. 82 DYNALLOC, 83 84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 85 /// at function entry, used for PIC code. 86 GlobalBaseReg, 87 88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 89 /// shift amounts. These nodes are generated by the multi-precision shift 90 /// code. 91 SRL, SRA, SHL, 92 93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 94 /// registers. 95 EXTSW_32, 96 97 /// CALL - A direct function call. 98 /// CALL_NOP_SVR4 is a call with the special NOP which follows 64-bit 99 /// SVR4 calls. 100 CALL_Darwin, CALL_SVR4, CALL_NOP_SVR4, 101 102 /// NOP - Special NOP which follows 64-bit SVR4 calls. 103 NOP, 104 105 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 106 /// MTCTR instruction. 107 MTCTR, 108 109 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 110 /// BCTRL instruction. 111 BCTRL_Darwin, BCTRL_SVR4, 112 113 /// Return with a flag operand, matched by 'blr' 114 RET_FLAG, 115 116 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF 117 /// instructions. This copies the bits corresponding to the specified 118 /// CRREG into the resultant GPR. Bits corresponding to other CR regs 119 /// are undefined. 120 MFCR, 121 122 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 123 /// instructions. For lack of better number, we use the opcode number 124 /// encoding for the OPC field to identify the compare. For example, 838 125 /// is VCMPGTSH. 126 VCMP, 127 128 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 129 /// altivec VCMP*o instructions. For lack of better number, we use the 130 /// opcode number encoding for the OPC field to identify the compare. For 131 /// example, 838 is VCMPGTSH. 132 VCMPo, 133 134 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 135 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 136 /// condition register to branch on, OPC is the branch opcode to use (e.g. 137 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 138 /// an optional input flag argument. 139 COND_BRANCH, 140 141 // The following 5 instructions are used only as part of the 142 // long double-to-int conversion sequence. 143 144 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the 145 /// register. 146 MFFS, 147 148 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR. 149 MTFSB0, 150 151 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR. 152 MTFSB1, 153 154 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with 155 /// rounding towards zero. It has flags added so it won't move past the 156 /// FPSCR-setting instructions. 157 FADDRTZ, 158 159 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. 160 MTFSF, 161 162 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 163 /// reserve indexed. This is used to implement atomic operations. 164 LARX, 165 166 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 167 /// indexed. This is used to implement atomic operations. 168 STCX, 169 170 /// TC_RETURN - A tail call return. 171 /// operand #0 chain 172 /// operand #1 callee (register or absolute) 173 /// operand #2 stack adjustment 174 /// operand #3 optional in flag 175 TC_RETURN, 176 177 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 178 CR6SET, 179 CR6UNSET, 180 181 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 182 /// TLS model, produces an ADDIS8 instruction that adds the GOT 183 /// base to sym@got@tprel@ha. 184 ADDIS_GOT_TPREL_HA, 185 186 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 187 /// TLS model, produces a LD instruction with base register G8RReg 188 /// and offset sym@got@tprel@l. This completes the addition that 189 /// finds the offset of "sym" relative to the thread pointer. 190 LD_GOT_TPREL_L, 191 192 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 193 /// model, produces an ADD instruction that adds the contents of 194 /// G8RReg to the thread pointer. Symbol contains a relocation 195 /// sym@tls which is to be replaced by the thread pointer and 196 /// identifies to the linker that the instruction is part of a 197 /// TLS sequence. 198 ADD_TLS, 199 200 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 201 /// model, produces an ADDIS8 instruction that adds the GOT base 202 /// register to sym@got@tlsgd@ha. 203 ADDIS_TLSGD_HA, 204 205 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 206 /// model, produces an ADDI8 instruction that adds G8RReg to 207 /// sym@got@tlsgd@l. 208 ADDI_TLSGD_L, 209 210 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS 211 /// model, produces a call to __tls_get_addr(sym@tlsgd). 212 GET_TLS_ADDR, 213 214 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 215 /// model, produces an ADDIS8 instruction that adds the GOT base 216 /// register to sym@got@tlsld@ha. 217 ADDIS_TLSLD_HA, 218 219 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 220 /// model, produces an ADDI8 instruction that adds G8RReg to 221 /// sym@got@tlsld@l. 222 ADDI_TLSLD_L, 223 224 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS 225 /// model, produces a call to __tls_get_addr(sym@tlsld). 226 GET_TLSLD_ADDR, 227 228 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 229 /// local-dynamic TLS model, produces an ADDIS8 instruction 230 /// that adds X3 to sym@dtprel@ha. The Chain operand is needed 231 /// to tie this in place following a copy to %X3 from the result 232 /// of a GET_TLSLD_ADDR. 233 ADDIS_DTPREL_HA, 234 235 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 236 /// model, produces an ADDI8 instruction that adds G8RReg to 237 /// sym@got@dtprel@l. 238 ADDI_DTPREL_L, 239 240 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 241 /// into an ADD of a VSPLTI with itself during instruction selection. 242 /// Necessary to avoid losing this optimization due to constant folds. 243 VADD_SPLAT, 244 245 /// STD_32 - This is the STD instruction for use with "32-bit" registers. 246 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE, 247 248 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 249 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 250 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 251 /// i32. 252 STBRX, 253 254 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 255 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 256 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 257 /// or i32. 258 LBRX, 259 260 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium code model, produces 261 /// an ADDIS8 instruction that adds the TOC base register to sym@toc@ha. 262 ADDIS_TOC_HA, 263 264 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium code model, produces a 265 /// LD instruction with base register G8RReg and offset sym@toc@l. 266 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 267 LD_TOC_L, 268 269 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 270 /// an ADDI8 instruction that adds G8RReg to sym@toc@l. 271 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 272 ADDI_TOC_L 273 }; 274 } 275 276 /// Define some predicates that are used for node matching. 277 namespace PPC { 278 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 279 /// VPKUHUM instruction. 280 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 281 282 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 283 /// VPKUWUM instruction. 284 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 285 286 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 287 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 288 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 289 bool isUnary); 290 291 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 292 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 293 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 294 bool isUnary); 295 296 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 297 /// amount, otherwise return -1. 298 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 299 300 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 301 /// specifies a splat of a single element that is suitable for input to 302 /// VSPLTB/VSPLTH/VSPLTW. 303 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 304 305 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 306 /// are -0.0. 307 bool isAllNegativeZeroVector(SDNode *N); 308 309 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 310 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 311 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 312 313 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 314 /// formed by using a vspltis[bhw] instruction of the specified element 315 /// size, return the constant being splatted. The ByteSize field indicates 316 /// the number of bytes of each element [124] -> [bhw]. 317 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 318 } 319 320 class PPCTargetLowering : public TargetLowering { 321 const PPCSubtarget &PPCSubTarget; 322 323 public: 324 explicit PPCTargetLowering(PPCTargetMachine &TM); 325 326 /// getTargetNodeName() - This method returns the name of a target specific 327 /// DAG node. 328 virtual const char *getTargetNodeName(unsigned Opcode) const; 329 330 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 331 332 /// getSetCCResultType - Return the ISD::SETCC ValueType 333 virtual EVT getSetCCResultType(EVT VT) const; 334 335 /// getPreIndexedAddressParts - returns true by value, base pointer and 336 /// offset pointer and addressing mode by reference if the node's address 337 /// can be legally represented as pre-indexed load / store address. 338 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 339 SDValue &Offset, 340 ISD::MemIndexedMode &AM, 341 SelectionDAG &DAG) const; 342 343 /// SelectAddressRegReg - Given the specified addressed, check to see if it 344 /// can be represented as an indexed [r+r] operation. Returns false if it 345 /// can be more efficiently represented with [r+imm]. 346 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 347 SelectionDAG &DAG) const; 348 349 /// SelectAddressRegImm - Returns true if the address N can be represented 350 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 351 /// is not better represented as reg+reg. 352 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 353 SelectionDAG &DAG) const; 354 355 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 356 /// represented as an indexed [r+r] operation. 357 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 358 SelectionDAG &DAG) const; 359 360 /// SelectAddressRegImmShift - Returns true if the address N can be 361 /// represented by a base register plus a signed 14-bit displacement 362 /// [r+imm*4]. Suitable for use by STD and friends. 363 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, 364 SelectionDAG &DAG) const; 365 366 Sched::Preference getSchedulingPreference(SDNode *N) const; 367 368 /// LowerOperation - Provide custom lowering hooks for some operations. 369 /// 370 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 371 372 /// ReplaceNodeResults - Replace the results of node with an illegal result 373 /// type with new values built out of custom code. 374 /// 375 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 376 SelectionDAG &DAG) const; 377 378 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 379 380 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 381 APInt &KnownZero, 382 APInt &KnownOne, 383 const SelectionDAG &DAG, 384 unsigned Depth = 0) const; 385 386 virtual MachineBasicBlock * 387 EmitInstrWithCustomInserter(MachineInstr *MI, 388 MachineBasicBlock *MBB) const; 389 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 390 MachineBasicBlock *MBB, bool is64Bit, 391 unsigned BinOpcode) const; 392 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 393 MachineBasicBlock *MBB, 394 bool is8bit, unsigned Opcode) const; 395 396 ConstraintType getConstraintType(const std::string &Constraint) const; 397 398 /// Examine constraint string and operand type and determine a weight value. 399 /// The operand object must already have been set up with the operand type. 400 ConstraintWeight getSingleConstraintMatchWeight( 401 AsmOperandInfo &info, const char *constraint) const; 402 403 std::pair<unsigned, const TargetRegisterClass*> 404 getRegForInlineAsmConstraint(const std::string &Constraint, 405 EVT VT) const; 406 407 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 408 /// function arguments in the caller parameter area. This is the actual 409 /// alignment, not its logarithm. 410 unsigned getByValTypeAlignment(Type *Ty) const; 411 412 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 413 /// vector. If it is invalid, don't add anything to Ops. 414 virtual void LowerAsmOperandForConstraint(SDValue Op, 415 std::string &Constraint, 416 std::vector<SDValue> &Ops, 417 SelectionDAG &DAG) const; 418 419 /// isLegalAddressingMode - Return true if the addressing mode represented 420 /// by AM is legal for this target, for a load/store of the specified type. 421 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 422 423 /// isLegalAddressImmediate - Return true if the integer value can be used 424 /// as the offset of the target addressing mode for load / store of the 425 /// given type. 426 virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const; 427 428 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 429 /// the offset of the target addressing mode. 430 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 431 432 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 433 434 /// getOptimalMemOpType - Returns the target specific optimal type for load 435 /// and store operations as a result of memset, memcpy, and memmove 436 /// lowering. If DstAlign is zero that means it's safe to destination 437 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 438 /// means there isn't a need to check it against alignment requirement, 439 /// probably because the source does not need to be loaded. If 'IsMemset' is 440 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 441 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 442 /// source is constant so it does not need to be loaded. 443 /// It returns EVT::Other if the type should be determined using generic 444 /// target-independent logic. 445 virtual EVT 446 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 447 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 448 MachineFunction &MF) const; 449 450 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 451 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 452 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 453 /// is expanded to mul + add. 454 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const; 455 456 private: 457 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 458 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 459 460 bool 461 IsEligibleForTailCallOptimization(SDValue Callee, 462 CallingConv::ID CalleeCC, 463 bool isVarArg, 464 const SmallVectorImpl<ISD::InputArg> &Ins, 465 SelectionDAG& DAG) const; 466 467 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 468 int SPDiff, 469 SDValue Chain, 470 SDValue &LROpOut, 471 SDValue &FPOpOut, 472 bool isDarwinABI, 473 DebugLoc dl) const; 474 475 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 476 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 477 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 478 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 479 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 480 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 481 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 482 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 483 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 484 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 485 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 486 const PPCSubtarget &Subtarget) const; 487 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 488 const PPCSubtarget &Subtarget) const; 489 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 490 const PPCSubtarget &Subtarget) const; 491 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 492 const PPCSubtarget &Subtarget) const; 493 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 494 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const; 495 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 496 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 497 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 498 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 499 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 500 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 501 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 502 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 503 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 504 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 505 506 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 507 CallingConv::ID CallConv, bool isVarArg, 508 const SmallVectorImpl<ISD::InputArg> &Ins, 509 DebugLoc dl, SelectionDAG &DAG, 510 SmallVectorImpl<SDValue> &InVals) const; 511 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, 512 bool isVarArg, 513 SelectionDAG &DAG, 514 SmallVector<std::pair<unsigned, SDValue>, 8> 515 &RegsToPass, 516 SDValue InFlag, SDValue Chain, 517 SDValue &Callee, 518 int SPDiff, unsigned NumBytes, 519 const SmallVectorImpl<ISD::InputArg> &Ins, 520 SmallVectorImpl<SDValue> &InVals) const; 521 522 virtual SDValue 523 LowerFormalArguments(SDValue Chain, 524 CallingConv::ID CallConv, bool isVarArg, 525 const SmallVectorImpl<ISD::InputArg> &Ins, 526 DebugLoc dl, SelectionDAG &DAG, 527 SmallVectorImpl<SDValue> &InVals) const; 528 529 virtual SDValue 530 LowerCall(TargetLowering::CallLoweringInfo &CLI, 531 SmallVectorImpl<SDValue> &InVals) const; 532 533 virtual bool 534 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 535 bool isVarArg, 536 const SmallVectorImpl<ISD::OutputArg> &Outs, 537 LLVMContext &Context) const; 538 539 virtual SDValue 540 LowerReturn(SDValue Chain, 541 CallingConv::ID CallConv, bool isVarArg, 542 const SmallVectorImpl<ISD::OutputArg> &Outs, 543 const SmallVectorImpl<SDValue> &OutVals, 544 DebugLoc dl, SelectionDAG &DAG) const; 545 546 SDValue 547 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 548 SDValue ArgVal, DebugLoc dl) const; 549 550 void 551 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 552 unsigned nAltivecParamsAtEnd, 553 unsigned MinReservedArea, bool isPPC64) const; 554 555 SDValue 556 LowerFormalArguments_Darwin(SDValue Chain, 557 CallingConv::ID CallConv, bool isVarArg, 558 const SmallVectorImpl<ISD::InputArg> &Ins, 559 DebugLoc dl, SelectionDAG &DAG, 560 SmallVectorImpl<SDValue> &InVals) const; 561 SDValue 562 LowerFormalArguments_64SVR4(SDValue Chain, 563 CallingConv::ID CallConv, bool isVarArg, 564 const SmallVectorImpl<ISD::InputArg> &Ins, 565 DebugLoc dl, SelectionDAG &DAG, 566 SmallVectorImpl<SDValue> &InVals) const; 567 SDValue 568 LowerFormalArguments_32SVR4(SDValue Chain, 569 CallingConv::ID CallConv, bool isVarArg, 570 const SmallVectorImpl<ISD::InputArg> &Ins, 571 DebugLoc dl, SelectionDAG &DAG, 572 SmallVectorImpl<SDValue> &InVals) const; 573 574 SDValue 575 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 576 SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 577 SelectionDAG &DAG, DebugLoc dl) const; 578 579 SDValue 580 LowerCall_Darwin(SDValue Chain, SDValue Callee, 581 CallingConv::ID CallConv, 582 bool isVarArg, bool isTailCall, 583 const SmallVectorImpl<ISD::OutputArg> &Outs, 584 const SmallVectorImpl<SDValue> &OutVals, 585 const SmallVectorImpl<ISD::InputArg> &Ins, 586 DebugLoc dl, SelectionDAG &DAG, 587 SmallVectorImpl<SDValue> &InVals) const; 588 SDValue 589 LowerCall_64SVR4(SDValue Chain, SDValue Callee, 590 CallingConv::ID CallConv, 591 bool isVarArg, bool isTailCall, 592 const SmallVectorImpl<ISD::OutputArg> &Outs, 593 const SmallVectorImpl<SDValue> &OutVals, 594 const SmallVectorImpl<ISD::InputArg> &Ins, 595 DebugLoc dl, SelectionDAG &DAG, 596 SmallVectorImpl<SDValue> &InVals) const; 597 SDValue 598 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 599 bool isVarArg, bool isTailCall, 600 const SmallVectorImpl<ISD::OutputArg> &Outs, 601 const SmallVectorImpl<SDValue> &OutVals, 602 const SmallVectorImpl<ISD::InputArg> &Ins, 603 DebugLoc dl, SelectionDAG &DAG, 604 SmallVectorImpl<SDValue> &InVals) const; 605 }; 606} 607 608#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 609