PPCISelLowering.h revision da43bcf624acb56a3d77bb5ae9a02728af032613
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "PPC.h" 21#include "PPCSubtarget.h" 22 23namespace llvm { 24 namespace PPCISD { 25 enum NodeType { 26 // Start the numbering where the builtin ops and target ops leave off. 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 29 /// FSEL - Traditional three-operand fsel node. 30 /// 31 FSEL, 32 33 /// FCFID - The FCFID instruction, taking an f64 operand and producing 34 /// and f64 value containing the FP representation of the integer that 35 /// was temporarily in the f64 operand. 36 FCFID, 37 38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 39 /// operand, producing an f64 value containing the integer representation 40 /// of that FP value. 41 FCTIDZ, FCTIWZ, 42 43 /// STFIWX - The STFIWX instruction. The first operand is an input token 44 /// chain, then an f64 value to store, then an address to store it to, 45 /// then a SRCVALUE for the address. 46 STFIWX, 47 48 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 49 // three v4f32 operands and producing a v4f32 result. 50 VMADDFP, VNMSUBFP, 51 52 /// VPERM - The PPC VPERM Instruction. 53 /// 54 VPERM, 55 56 /// Hi/Lo - These represent the high and low 16-bit parts of a global 57 /// address respectively. These nodes have two operands, the first of 58 /// which must be a TargetGlobalAddress, and the second of which must be a 59 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 60 /// though these are usually folded into other nodes. 61 Hi, Lo, 62 63 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 64 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 65 /// compute an allocation on the stack. 66 DYNALLOC, 67 68 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 69 /// at function entry, used for PIC code. 70 GlobalBaseReg, 71 72 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 73 /// shift amounts. These nodes are generated by the multi-precision shift 74 /// code. 75 SRL, SRA, SHL, 76 77 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 78 /// registers. 79 EXTSW_32, 80 81 /// STD_32 - This is the STD instruction for use with "32-bit" registers. 82 STD_32, 83 84 /// CALL - A direct function call. 85 CALL_Macho, CALL_ELF, 86 87 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 88 /// MTCTR instruction. 89 MTCTR, 90 91 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 92 /// BCTRL instruction. 93 BCTRL_Macho, BCTRL_ELF, 94 95 /// Return with a flag operand, matched by 'blr' 96 RET_FLAG, 97 98 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. 99 /// This copies the bits corresponding to the specified CRREG into the 100 /// resultant GPR. Bits corresponding to other CR regs are undefined. 101 MFCR, 102 103 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 104 /// instructions. For lack of better number, we use the opcode number 105 /// encoding for the OPC field to identify the compare. For example, 838 106 /// is VCMPGTSH. 107 VCMP, 108 109 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 110 /// altivec VCMP*o instructions. For lack of better number, we use the 111 /// opcode number encoding for the OPC field to identify the compare. For 112 /// example, 838 is VCMPGTSH. 113 VCMPo, 114 115 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 116 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 117 /// condition register to branch on, OPC is the branch opcode to use (e.g. 118 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 119 /// an optional input flag argument. 120 COND_BRANCH, 121 122 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a 123 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 124 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 125 /// i32. 126 STBRX, 127 128 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a 129 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 130 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 131 /// or i32. 132 LBRX, 133 134 // The following 5 instructions are used only as part of the 135 // long double-to-int conversion sequence. 136 137 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the 138 /// register. 139 MFFS, 140 141 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR. 142 MTFSB0, 143 144 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR. 145 MTFSB1, 146 147 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with 148 /// rounding towards zero. It has flags added so it won't move past the 149 /// FPSCR-setting instructions. 150 FADDRTZ, 151 152 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. 153 MTFSF, 154 155 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 156 /// reserve indexed. This is used to implement atomic operations. 157 LARX, 158 159 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 160 /// indexed. This is used to implement atomic operations. 161 STCX, 162 163 /// TAILCALL - Indicates a tail call should be taken. 164 TAILCALL, 165 /// TC_RETURN - A tail call return. 166 /// operand #0 chain 167 /// operand #1 callee (register or absolute) 168 /// operand #2 stack adjustment 169 /// operand #3 optional in flag 170 TC_RETURN 171 }; 172 } 173 174 /// Define some predicates that are used for node matching. 175 namespace PPC { 176 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 177 /// VPKUHUM instruction. 178 bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary); 179 180 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 181 /// VPKUWUM instruction. 182 bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary); 183 184 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 185 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 186 bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 187 188 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 189 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 190 bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 191 192 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 193 /// amount, otherwise return -1. 194 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 195 196 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 197 /// specifies a splat of a single element that is suitable for input to 198 /// VSPLTB/VSPLTH/VSPLTW. 199 bool isSplatShuffleMask(SDNode *N, unsigned EltSize); 200 201 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 202 /// are -0.0. 203 bool isAllNegativeZeroVector(SDNode *N); 204 205 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 206 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 207 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 208 209 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 210 /// formed by using a vspltis[bhw] instruction of the specified element 211 /// size, return the constant being splatted. The ByteSize field indicates 212 /// the number of bytes of each element [124] -> [bhw]. 213 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 214 } 215 216 class PPCTargetLowering : public TargetLowering { 217 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 218 int VarArgsStackOffset; // StackOffset for start of stack 219 // arguments. 220 unsigned VarArgsNumGPR; // Index of the first unused integer 221 // register for parameter passing. 222 unsigned VarArgsNumFPR; // Index of the first unused double 223 // register for parameter passing. 224 int ReturnAddrIndex; // FrameIndex for return slot. 225 const PPCSubtarget &PPCSubTarget; 226 public: 227 explicit PPCTargetLowering(PPCTargetMachine &TM); 228 229 /// getTargetNodeName() - This method returns the name of a target specific 230 /// DAG node. 231 virtual const char *getTargetNodeName(unsigned Opcode) const; 232 233 /// getSetCCResultType - Return the ISD::SETCC ValueType 234 virtual MVT getSetCCResultType(const SDValue &) const; 235 236 /// getPreIndexedAddressParts - returns true by value, base pointer and 237 /// offset pointer and addressing mode by reference if the node's address 238 /// can be legally represented as pre-indexed load / store address. 239 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 240 SDValue &Offset, 241 ISD::MemIndexedMode &AM, 242 SelectionDAG &DAG); 243 244 /// SelectAddressRegReg - Given the specified addressed, check to see if it 245 /// can be represented as an indexed [r+r] operation. Returns false if it 246 /// can be more efficiently represented with [r+imm]. 247 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 248 SelectionDAG &DAG); 249 250 /// SelectAddressRegImm - Returns true if the address N can be represented 251 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 252 /// is not better represented as reg+reg. 253 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 254 SelectionDAG &DAG); 255 256 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 257 /// represented as an indexed [r+r] operation. 258 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 259 SelectionDAG &DAG); 260 261 /// SelectAddressRegImmShift - Returns true if the address N can be 262 /// represented by a base register plus a signed 14-bit displacement 263 /// [r+imm*4]. Suitable for use by STD and friends. 264 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, 265 SelectionDAG &DAG); 266 267 268 /// LowerOperation - Provide custom lowering hooks for some operations. 269 /// 270 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 271 272 virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG); 273 274 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 275 276 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 277 const APInt &Mask, 278 APInt &KnownZero, 279 APInt &KnownOne, 280 const SelectionDAG &DAG, 281 unsigned Depth = 0) const; 282 283 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 284 MachineBasicBlock *MBB); 285 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 286 MachineBasicBlock *MBB, bool is64Bit, 287 unsigned BinOpcode); 288 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 289 MachineBasicBlock *MBB, 290 bool is8bit, unsigned Opcode); 291 292 ConstraintType getConstraintType(const std::string &Constraint) const; 293 std::pair<unsigned, const TargetRegisterClass*> 294 getRegForInlineAsmConstraint(const std::string &Constraint, 295 MVT VT) const; 296 297 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 298 /// function arguments in the caller parameter area. This is the actual 299 /// alignment, not its logarithm. 300 unsigned getByValTypeAlignment(const Type *Ty) const; 301 302 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 303 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 304 /// true it means one of the asm constraint of the inline asm instruction 305 /// being processed is 'm'. 306 virtual void LowerAsmOperandForConstraint(SDValue Op, 307 char ConstraintLetter, 308 bool hasMemory, 309 std::vector<SDValue> &Ops, 310 SelectionDAG &DAG) const; 311 312 /// isLegalAddressingMode - Return true if the addressing mode represented 313 /// by AM is legal for this target, for a load/store of the specified type. 314 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 315 316 /// isLegalAddressImmediate - Return true if the integer value can be used 317 /// as the offset of the target addressing mode for load / store of the 318 /// given type. 319 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; 320 321 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 322 /// the offset of the target addressing mode. 323 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 324 325 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 326 /// for tail call optimization. Target which want to do tail call 327 /// optimization should implement this function. 328 virtual bool IsEligibleForTailCallOptimization(CallSDNode *TheCall, 329 SDValue Ret, 330 SelectionDAG &DAG) const; 331 332 private: 333 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 334 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 335 336 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 337 int SPDiff, 338 SDValue Chain, 339 SDValue &LROpOut, 340 SDValue &FPOpOut); 341 342 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 343 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 344 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 345 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 346 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 347 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 348 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 349 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 350 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 351 int VarArgsFrameIndex, int VarArgsStackOffset, 352 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, 353 const PPCSubtarget &Subtarget); 354 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex, 355 int VarArgsStackOffset, unsigned VarArgsNumGPR, 356 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget); 357 SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, 358 int &VarArgsFrameIndex, 359 int &VarArgsStackOffset, 360 unsigned &VarArgsNumGPR, 361 unsigned &VarArgsNumFPR, 362 const PPCSubtarget &Subtarget); 363 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG, 364 const PPCSubtarget &Subtarget, TargetMachine &TM); 365 SDValue LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM); 366 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 367 const PPCSubtarget &Subtarget); 368 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 369 const PPCSubtarget &Subtarget); 370 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); 371 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); 372 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 373 SDValue LowerFP_ROUND_INREG(SDValue Op, SelectionDAG &DAG); 374 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 375 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG); 376 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG); 377 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG); 378 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 379 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 380 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 381 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 382 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG); 383 }; 384} 385 386#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 387