PPCISelLowering.h revision e87192a854ff0f2f1904dd9ea282eb36059bb5af
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "PPC.h" 21 22namespace llvm { 23 namespace PPCISD { 24 enum NodeType { 25 // Start the numbering where the builting ops and target ops leave off. 26 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END, 27 28 /// FSEL - Traditional three-operand fsel node. 29 /// 30 FSEL, 31 32 /// FCFID - The FCFID instruction, taking an f64 operand and producing 33 /// and f64 value containing the FP representation of the integer that 34 /// was temporarily in the f64 operand. 35 FCFID, 36 37 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 38 /// operand, producing an f64 value containing the integer representation 39 /// of that FP value. 40 FCTIDZ, FCTIWZ, 41 42 /// STFIWX - The STFIWX instruction. The first operand is an input token 43 /// chain, then an f64 value to store, then an address to store it to, 44 /// then a SRCVALUE for the address. 45 STFIWX, 46 47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 48 // three v4f32 operands and producing a v4f32 result. 49 VMADDFP, VNMSUBFP, 50 51 /// VPERM - The PPC VPERM Instruction. 52 /// 53 VPERM, 54 55 /// Hi/Lo - These represent the high and low 16-bit parts of a global 56 /// address respectively. These nodes have two operands, the first of 57 /// which must be a TargetGlobalAddress, and the second of which must be a 58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 59 /// though these are usually folded into other nodes. 60 Hi, Lo, 61 62 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 63 /// at function entry, used for PIC code. 64 GlobalBaseReg, 65 66 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 67 /// shift amounts. These nodes are generated by the multi-precision shift 68 /// code. 69 SRL, SRA, SHL, 70 71 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 72 /// registers. 73 EXTSW_32, 74 75 /// STD_32 - This is the STD instruction for use with "32-bit" registers. 76 STD_32, 77 78 /// CALL - A function call. 79 CALL, 80 81 /// Return with a flag operand, matched by 'blr' 82 RET_FLAG, 83 84 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. 85 /// This copies the bits corresponding to the specified CRREG into the 86 /// resultant GPR. Bits corresponding to other CR regs are undefined. 87 MFCR, 88 89 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 90 /// instructions. For lack of better number, we use the opcode number 91 /// encoding for the OPC field to identify the compare. For example, 838 92 /// is VCMPGTSH. 93 VCMP, 94 95 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 96 /// altivec VCMP*o instructions. For lack of better number, we use the 97 /// opcode number encoding for the OPC field to identify the compare. For 98 /// example, 838 is VCMPGTSH. 99 VCMPo 100 }; 101 } 102 103 /// Define some predicates that are used for node matching. 104 namespace PPC { 105 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 106 /// VPKUHUM instruction. 107 bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary); 108 109 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 110 /// VPKUWUM instruction. 111 bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary); 112 113 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 114 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 115 bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 116 117 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 118 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 119 bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 120 121 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 122 /// amount, otherwise return -1. 123 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 124 125 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 126 /// specifies a splat of a single element that is suitable for input to 127 /// VSPLTB/VSPLTH/VSPLTW. 128 bool isSplatShuffleMask(SDNode *N, unsigned EltSize); 129 130 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 131 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 132 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 133 134 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 135 /// formed by using a vspltis[bhw] instruction of the specified element 136 /// size, return the constant being splatted. The ByteSize field indicates 137 /// the number of bytes of each element [124] -> [bhw]. 138 SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 139 } 140 141 class PPCTargetLowering : public TargetLowering { 142 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 143 int ReturnAddrIndex; // FrameIndex for return slot. 144 public: 145 PPCTargetLowering(TargetMachine &TM); 146 147 /// getTargetNodeName() - This method returns the name of a target specific 148 /// DAG node. 149 virtual const char *getTargetNodeName(unsigned Opcode) const; 150 151 /// LowerOperation - Provide custom lowering hooks for some operations. 152 /// 153 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 154 155 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 156 157 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 158 uint64_t Mask, 159 uint64_t &KnownZero, 160 uint64_t &KnownOne, 161 unsigned Depth = 0) const; 162 /// LowerArguments - This hook must be implemented to indicate how we should 163 /// lower the arguments for the specified function, into the specified DAG. 164 virtual std::vector<SDOperand> 165 LowerArguments(Function &F, SelectionDAG &DAG); 166 167 /// LowerCallTo - This hook lowers an abstract call to a function into an 168 /// actual call. 169 virtual std::pair<SDOperand, SDOperand> 170 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 171 unsigned CC, 172 bool isTailCall, SDOperand Callee, ArgListTy &Args, 173 SelectionDAG &DAG); 174 175 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 176 MachineBasicBlock *MBB); 177 178 ConstraintType getConstraintType(char ConstraintLetter) const; 179 std::vector<unsigned> 180 getRegClassForInlineAsmConstraint(const std::string &Constraint, 181 MVT::ValueType VT) const; 182 bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); 183 184 /// isLegalAddressImmediate - Return true if the integer value can be used 185 /// as the offset of the target addressing mode. 186 virtual bool isLegalAddressImmediate(int64_t V) const; 187 }; 188} 189 190#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 191