1//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15#define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
16
17#include "PPCFrameLowering.h"
18#include "PPCISelLowering.h"
19#include "PPCInstrInfo.h"
20#include "llvm/ADT/Triple.h"
21#include "llvm/IR/DataLayout.h"
22#include "llvm/MC/MCInstrItineraries.h"
23#include "llvm/Target/TargetSelectionDAGInfo.h"
24#include "llvm/Target/TargetSubtargetInfo.h"
25#include <string>
26
27#define GET_SUBTARGETINFO_HEADER
28#include "PPCGenSubtargetInfo.inc"
29
30// GCC #defines PPC on Linux but we use it as our namespace name
31#undef PPC
32
33namespace llvm {
34class StringRef;
35
36namespace PPC {
37  // -m directive values.
38  enum {
39    DIR_NONE,
40    DIR_32,
41    DIR_440,
42    DIR_601,
43    DIR_602,
44    DIR_603,
45    DIR_7400,
46    DIR_750,
47    DIR_970,
48    DIR_A2,
49    DIR_E500mc,
50    DIR_E5500,
51    DIR_PWR3,
52    DIR_PWR4,
53    DIR_PWR5,
54    DIR_PWR5X,
55    DIR_PWR6,
56    DIR_PWR6X,
57    DIR_PWR7,
58    DIR_PWR8,
59    DIR_64
60  };
61}
62
63class GlobalValue;
64class TargetMachine;
65
66class PPCSubtarget : public PPCGenSubtargetInfo {
67protected:
68  /// TargetTriple - What processor and OS we're targeting.
69  Triple TargetTriple;
70
71  /// stackAlignment - The minimum alignment known to hold of the stack frame on
72  /// entry to the function and which must be maintained by every function.
73  unsigned StackAlignment;
74
75  /// Selected instruction itineraries (one entry per itinerary class.)
76  InstrItineraryData InstrItins;
77
78  /// Which cpu directive was used.
79  unsigned DarwinDirective;
80
81  /// Used by the ISel to turn in optimizations for POWER4-derived architectures
82  bool HasMFOCRF;
83  bool Has64BitSupport;
84  bool Use64BitRegs;
85  bool UseCRBits;
86  bool UseSoftFloat;
87  bool IsPPC64;
88  bool HasAltivec;
89  bool HasSPE;
90  bool HasQPX;
91  bool HasVSX;
92  bool HasP8Vector;
93  bool HasP8Altivec;
94  bool HasP8Crypto;
95  bool HasFCPSGN;
96  bool HasFSQRT;
97  bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
98  bool HasRecipPrec;
99  bool HasSTFIWX;
100  bool HasLFIWAX;
101  bool HasFPRND;
102  bool HasFPCVT;
103  bool HasISEL;
104  bool HasPOPCNTD;
105  bool HasBPERMD;
106  bool HasExtDiv;
107  bool HasCMPB;
108  bool HasLDBRX;
109  bool IsBookE;
110  bool HasOnlyMSYNC;
111  bool IsE500;
112  bool IsPPC4xx;
113  bool IsPPC6xx;
114  bool FeatureMFTB;
115  bool DeprecatedDST;
116  bool HasLazyResolverStubs;
117  bool IsLittleEndian;
118  bool HasICBT;
119  bool HasInvariantFunctionDescriptors;
120  bool HasPartwordAtomics;
121  bool HasDirectMove;
122  bool HasHTM;
123  bool HasFusion;
124  bool HasFloat128;
125
126  /// When targeting QPX running a stock PPC64 Linux kernel where the stack
127  /// alignment has not been changed, we need to keep the 16-byte alignment
128  /// of the stack.
129  bool IsQPXStackUnaligned;
130
131  const PPCTargetMachine &TM;
132  PPCFrameLowering FrameLowering;
133  PPCInstrInfo InstrInfo;
134  PPCTargetLowering TLInfo;
135  TargetSelectionDAGInfo TSInfo;
136
137public:
138  /// This constructor initializes the data members to match that
139  /// of the specified triple.
140  ///
141  PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
142               const PPCTargetMachine &TM);
143
144  /// ParseSubtargetFeatures - Parses features string setting specified
145  /// subtarget options.  Definition of function is auto generated by tblgen.
146  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
147
148  /// getStackAlignment - Returns the minimum alignment known to hold of the
149  /// stack frame on entry to the function and which must be maintained by every
150  /// function for this subtarget.
151  unsigned getStackAlignment() const { return StackAlignment; }
152
153  /// getDarwinDirective - Returns the -m directive specified for the cpu.
154  ///
155  unsigned getDarwinDirective() const { return DarwinDirective; }
156
157  /// getInstrItins - Return the instruction itineraries based on subtarget
158  /// selection.
159  const InstrItineraryData *getInstrItineraryData() const override {
160    return &InstrItins;
161  }
162
163  const PPCFrameLowering *getFrameLowering() const override {
164    return &FrameLowering;
165  }
166  const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
167  const PPCTargetLowering *getTargetLowering() const override {
168    return &TLInfo;
169  }
170  const TargetSelectionDAGInfo *getSelectionDAGInfo() const override {
171    return &TSInfo;
172  }
173  const PPCRegisterInfo *getRegisterInfo() const override {
174    return &getInstrInfo()->getRegisterInfo();
175  }
176  const PPCTargetMachine &getTargetMachine() const { return TM; }
177
178  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
179  /// so that we can use initializer lists for subtarget initialization.
180  PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
181
182private:
183  void initializeEnvironment();
184  void initSubtargetFeatures(StringRef CPU, StringRef FS);
185
186public:
187  /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
188  ///
189  bool isPPC64() const;
190
191  /// has64BitSupport - Return true if the selected CPU supports 64-bit
192  /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
193  bool has64BitSupport() const { return Has64BitSupport; }
194  // useSoftFloat - Return true if soft-float option is turned on.
195  bool useSoftFloat() const { return UseSoftFloat; }
196
197  /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
198  /// registers in 32-bit mode when possible.  This can only true if
199  /// has64BitSupport() returns true.
200  bool use64BitRegs() const { return Use64BitRegs; }
201
202  /// useCRBits - Return true if we should store and manipulate i1 values in
203  /// the individual condition register bits.
204  bool useCRBits() const { return UseCRBits; }
205
206  /// hasLazyResolverStub - Return true if accesses to the specified global have
207  /// to go through a dyld lazy resolution stub.  This means that an extra load
208  /// is required to get the address of the global.
209  bool hasLazyResolverStub(const GlobalValue *GV) const;
210
211  // isLittleEndian - True if generating little-endian code
212  bool isLittleEndian() const { return IsLittleEndian; }
213
214  // Specific obvious features.
215  bool hasFCPSGN() const { return HasFCPSGN; }
216  bool hasFSQRT() const { return HasFSQRT; }
217  bool hasFRE() const { return HasFRE; }
218  bool hasFRES() const { return HasFRES; }
219  bool hasFRSQRTE() const { return HasFRSQRTE; }
220  bool hasFRSQRTES() const { return HasFRSQRTES; }
221  bool hasRecipPrec() const { return HasRecipPrec; }
222  bool hasSTFIWX() const { return HasSTFIWX; }
223  bool hasLFIWAX() const { return HasLFIWAX; }
224  bool hasFPRND() const { return HasFPRND; }
225  bool hasFPCVT() const { return HasFPCVT; }
226  bool hasAltivec() const { return HasAltivec; }
227  bool hasSPE() const { return HasSPE; }
228  bool hasQPX() const { return HasQPX; }
229  bool hasVSX() const { return HasVSX; }
230  bool hasP8Vector() const { return HasP8Vector; }
231  bool hasP8Altivec() const { return HasP8Altivec; }
232  bool hasP8Crypto() const { return HasP8Crypto; }
233  bool hasMFOCRF() const { return HasMFOCRF; }
234  bool hasISEL() const { return HasISEL; }
235  bool hasPOPCNTD() const { return HasPOPCNTD; }
236  bool hasBPERMD() const { return HasBPERMD; }
237  bool hasExtDiv() const { return HasExtDiv; }
238  bool hasCMPB() const { return HasCMPB; }
239  bool hasLDBRX() const { return HasLDBRX; }
240  bool isBookE() const { return IsBookE; }
241  bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
242  bool isPPC4xx() const { return IsPPC4xx; }
243  bool isPPC6xx() const { return IsPPC6xx; }
244  bool isE500() const { return IsE500; }
245  bool isFeatureMFTB() const { return FeatureMFTB; }
246  bool isDeprecatedDST() const { return DeprecatedDST; }
247  bool hasICBT() const { return HasICBT; }
248  bool hasInvariantFunctionDescriptors() const {
249    return HasInvariantFunctionDescriptors;
250  }
251  bool hasPartwordAtomics() const { return HasPartwordAtomics; }
252  bool hasDirectMove() const { return HasDirectMove; }
253
254  bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
255  unsigned getPlatformStackAlignment() const {
256    if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
257      return 32;
258
259    return 16;
260  }
261  bool hasHTM() const { return HasHTM; }
262  bool hasFusion() const { return HasFusion; }
263  bool hasFloat128() const { return HasFloat128; }
264
265  const Triple &getTargetTriple() const { return TargetTriple; }
266
267  /// isDarwin - True if this is any darwin platform.
268  bool isDarwin() const { return TargetTriple.isMacOSX(); }
269  /// isBGQ - True if this is a BG/Q platform.
270  bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
271
272  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
273  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
274
275  bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
276  bool isSVR4ABI() const { return !isDarwinABI(); }
277  bool isELFv2ABI() const;
278
279  bool enableEarlyIfConversion() const override { return hasISEL(); }
280
281  // Scheduling customization.
282  bool enableMachineScheduler() const override;
283  // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
284  bool enablePostRAScheduler() const override;
285  AntiDepBreakMode getAntiDepBreakMode() const override;
286  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
287
288  void overrideSchedPolicy(MachineSchedPolicy &Policy,
289                           MachineInstr *begin,
290                           MachineInstr *end,
291                           unsigned NumRegionInstrs) const override;
292  bool useAA() const override;
293
294  bool enableSubRegLiveness() const override;
295
296  /// classifyGlobalReference - Classify a global variable reference for the
297  /// current subtarget accourding to how we should reference it.
298  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
299};
300} // End llvm namespace
301
302#endif
303