Searched defs:Slot (Results 1 - 25 of 45) sorted by relevance

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/external/libchrome/base/threading/
H A Dthread_local_storage.h25 // interface, you should instead be using ThreadLocalStorage::StaticSlot/Slot.
98 // ThreadLocalStorage::Slot (below) instead.
130 class BASE_EXPORT Slot : public StaticSlot { class in class:base::internal::ThreadLocalStorage
133 explicit Slot(TLSDestructorFunc destructor = NULL);
139 DISALLOW_COPY_AND_ASSIGN(Slot);
H A Dthread_local_storage.cc27 // assigned to the instance variable slot_ in a ThreadLocalStorage::Slot
29 // instance of ThreadLocalStorage::Slot has been freed (i.e., destructor called,
197 ThreadLocalStorage::Slot::Slot(TLSDestructorFunc destructor) { function in class:base::ThreadLocalStorage::Slot
/external/llvm/lib/CodeGen/
H A DLiveStackAnalysis.cpp1 //===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
31 "Live Stack Slot Analysis", false, false)
34 "Live Stack Slot Analysis", false, false)
60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
61 assert(Slot >= 0 && "Spill slot indice must be >= 0");
62 SS2IntervalMap::iterator I = S2IMap.find(Slot);
64 I = S2IMap.emplace(std::piecewise_construct, std::forward_as_tuple(Slot),
66 TargetRegisterInfo::index2StackSlot(Slot), 0.0F))
68 S2RCMap.insert(std::make_pair(Slot, RC));
71 const TargetRegisterClass *OldRC = S2RCMap[Slot];
83 int Slot = I->first; local
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H A DMIRPrinter.cpp353 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
430 int Slot = MST.getLocalSlot(BB); local
431 if (Slot == -1)
434 OS << (Twine("%ir-block.") + Twine(Slot)).str();
589 static void printIRSlotNumber(raw_ostream &OS, int Slot) { argument
590 if (Slot == -1)
593 OS << Slot; local
603 int Slot; local
605 Slot = MST.getLocalSlot(&BB);
610 Slot
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H A DStackColoring.cpp254 unsigned Slot = MO.getIndex(); local
258 const AllocaInst *Allocation = MFI->getObjectAllocation(Slot);
260 DEBUG(dbgs()<<"Found a lifetime marker for slot #"<<Slot<<
265 BlockInfo.Begin.set(Slot);
267 if (BlockInfo.Begin.test(Slot)) {
271 BlockInfo.Begin.reset(Slot);
273 BlockInfo.End.set(Slot);
393 int Slot = Mo.getIndex(); local
394 assert(Slot >= 0 && "Invalid slot");
399 if (!Starts[Slot]
599 int Slot = MO.getIndex(); local
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/external/llvm/lib/Transforms/Utils/
H A DDemoteRegToStack.cpp32 AllocaInst *Slot; local
34 Slot = new AllocaInst(I.getType(), nullptr,
38 Slot = new AllocaInst(I.getType(), nullptr, I.getName() + ".reg2mem",
74 V = new LoadInst(Slot, I.getName()+".reload", VolatileLoads,
82 Value *V = new LoadInst(Slot, I.getName()+".reload", VolatileLoads, U);
100 new StoreInst(&I, Slot, &*InsertPt);
101 return Slot;
114 AllocaInst *Slot; local
116 Slot = new AllocaInst(P->getType(), nullptr,
120 Slot
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/external/llvm/include/llvm/CodeGen/
H A DLiveStackAnalysis.h1 //===-- LiveStackAnalysis.h - Live Stack Slot Analysis ----------*- C++ -*-===//
58 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
60 LiveInterval &getInterval(int Slot) { argument
61 assert(Slot >= 0 && "Spill slot indice must be >= 0");
62 SS2IntervalMap::iterator I = S2IMap.find(Slot);
67 const LiveInterval &getInterval(int Slot) const {
68 assert(Slot >= 0 && "Spill slot indice must be >= 0");
69 SS2IntervalMap::const_iterator I = S2IMap.find(Slot);
74 bool hasInterval(int Slot) const { return S2IMap.count(Slot); }
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H A DMachineModuleInfo.h194 unsigned Slot; member in struct:llvm::MachineModuleInfo::VariableDbgInfo
198 unsigned Slot, const DILocation *Loc)
199 : Var(Var), Expr(Expr), Slot(Slot), Loc(Loc) {}
422 unsigned Slot, const DILocation *Loc) {
423 VariableDbgInfos.emplace_back(Var, Expr, Slot, Loc);
197 VariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr, unsigned Slot, const DILocation *Loc) argument
421 setVariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr, unsigned Slot, const DILocation *Loc) argument
H A DSlotIndexes.h1 //===- llvm/CodeGen/SlotIndexes.h - Slot indexes representation -*- C++ -*-===//
95 enum Slot { enum in class:llvm::SlotIndex
138 Slot getSlot() const {
139 return static_cast<Slot>(lie.getInt());
153 SlotIndex(const SlotIndex &li, Slot s) : lie(li.listEntry(), unsigned(s)) {
273 Slot s = getSlot();
293 Slot s = getSlot();
/external/llvm/lib/Transforms/IPO/
H A DConstantMerge.cpp148 GlobalVariable *&Slot = CMap[Init]; local
153 if (!Slot || IsBetterCanonical(*GV, *Slot))
154 Slot = GV;
179 GlobalVariable *Slot = CMap[Init]; local
181 if (!Slot || Slot == GV)
184 if (!Slot->hasUnnamedAddr() && !GV->hasUnnamedAddr())
188 Slot->setUnnamedAddr(false);
191 Replacements.push_back(std::make_pair(GV, Slot));
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/external/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp350 DEBUG(dbgs() << "New Slot\n");
351 assert (OccupedSlotsMask && "Slot wasn't filled");
359 void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) { argument
374 // Constrains the regclass of DestReg to assign it to Slot
375 switch (Slot) {
391 SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot, bool AnyAlu) { argument
393 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu);
398 AssignSlot(UnslotedSU->getInstr(), Slot);
H A DR600InstrInfo.cpp434 llvm_unreachable("Wrong Swizzle for Trans Slot");
1225 return Ops[Slot]; \
1228 static unsigned getSlotedOps(unsigned Op, unsigned Slot) { argument
1255 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
1265 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
1267 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
1288 getSlotedOps(AMDGPU::OpName::pred_sel, Slot)));
1294 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1254 buildSlotOfVectorInstruction( MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const argument
/external/skia/include/private/
H A DSkTHash.h39 size_t approxBytesUsed() const { return fCapacity * sizeof(Slot); }
65 Slot& s = fSlots[index];
85 Slot& s = fSlots[index];
124 Slot& s = fSlots[index];
153 SkAutoTArray<Slot> oldSlots(capacity);
157 const Slot& s = oldSlots[i];
177 struct Slot { struct in class:SkTHashTable
178 Slot() : hash(0) {} function in struct:SkTHashTable::Slot
189 SkAutoTArray<Slot> fSlots;
/external/v8/test/unittests/compiler/
H A Dinstruction-sequence-unittest.h74 static TestOperand Slot(VReg vreg, int index = kNoValue) { function in class:v8::internal::compiler::InstructionSequenceTest
80 static TestOperand Slot(int index = kNoValue) { return Slot(VReg(), index); } function in class:v8::internal::compiler::InstructionSequenceTest
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp134 unsigned Slot = 0; local
135 for (unsigned e = Vals.size(); e - Slot > 2; Slot += 2, e += 1) {
138 SDValue LHS = Vals[Slot];
139 SDValue RHS = Vals[Slot + 1];
150 Lo = Vals[Slot++];
151 Hi = Vals[Slot++];
/external/llvm/lib/IR/
H A DAttributes.cpp1073 AttributeSet::iterator AttributeSet::begin(unsigned Slot) const {
1076 return pImpl->begin(Slot);
1079 AttributeSet::iterator AttributeSet::end(unsigned Slot) const {
1082 return pImpl->end(Slot);
1096 unsigned AttributeSet::getSlotIndex(unsigned Slot) const {
1097 assert(pImpl && Slot < pImpl->getNumAttributes() &&
1098 "Slot # out of range!");
1099 return pImpl->getSlotIndex(Slot);
1102 AttributeSet AttributeSet::getSlotAttributes(unsigned Slot) const {
1103 assert(pImpl && Slot < pImp
1207 unsigned Slot = ~0U; local
1342 unsigned Slot = ~0U; local
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/external/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
174 return "Mips Delay Slot Filler";
216 RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot,
221 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
225 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
230 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
651 RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot,
698 unsigned Opcode = (*Slot).getOpcode();
711 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
720 RegDU.init(*Slot);
650 searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot, IterTy &Filler) const argument
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/external/chromium-trace/catapult/third_party/pipeline/pipeline/
H A Dpipeline.py23 'UnexpectedPipelineError', 'PipelineStatusError', 'Slot', 'Pipeline',
172 class Slot(object): class in inherits:object
182 strict: If this Slot was created as an output of a strictly defined
186 raise UnexpectedPipelineError('Slot with key "%s" missing a name.' %
213 raise SlotNotFilledError('Slot with name "%s", key "%s" not yet filled.'
228 raise SlotNotFilledError('Slot with name "%s", key "%s" not yet filled.'
243 raise SlotNotFilledError('Slot with name "%s", key "%s" not yet filled.'
253 slot_record: The _SlotRecord containing this Slot's value.
282 return 'Slot(name="%s", slot_key="%s")' % (self.name, self.key)
304 'default': Slot(nam
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/external/clang/lib/CodeGen/
H A DCGVTables.cpp318 ReturnValueSlot Slot; local
322 Slot = ReturnValueSlot(ReturnValue, ResultType.isVolatileQualified());
326 RValue RV = EmitCall(*CurFnInfo, Callee, Slot, CallArgs, MD, &CallOrInvoke);
335 if (!ResultType->isVoidType() && Slot.isNull())
H A DCGAtomic.cpp1305 AggValueSlot Slot) {
1314 return EmitAtomicLoad(LV, SL, AO, IsVolatile, Slot);
1813 AggValueSlot Slot) {
1304 EmitAtomicLoad(LValue LV, SourceLocation SL, AggValueSlot Slot) argument
1810 EmitAtomicCompareExchange( LValue Obj, RValue Expected, RValue Desired, SourceLocation Loc, llvm::AtomicOrdering Success, llvm::AtomicOrdering Failure, bool IsWeak, AggValueSlot Slot) argument
H A DCGBlocks.cpp828 AggValueSlot Slot = local
833 EmitAggExpr(copyExpr, Slot);
H A DCGExprAgg.cpp555 AggValueSlot Slot = EnsureSlot(E->getType()); local
556 CGF.EmitAggExpr(E->getInitializer(), Slot);
999 AggValueSlot Slot = EnsureSlot(E->getType()); local
1000 CGF.EmitCXXConstructExpr(E, Slot);
1005 AggValueSlot Slot = EnsureSlot(E->getType()); local
1006 CGF.EmitLambdaExpr(E, Slot);
1017 AggValueSlot Slot = EnsureSlot(T); local
1018 EmitNullInitializationToLValue(CGF.MakeAddrLValue(Slot.getAddress(), T));
1023 AggValueSlot Slot = EnsureSlot(T); local
1024 EmitNullInitializationToLValue(CGF.MakeAddrLValue(Slot
1355 CheckAggExprForMemSetUse(AggValueSlot &Slot, const Expr *E, CodeGenFunction &CGF) argument
1400 EmitAggExpr(const Expr *E, AggValueSlot Slot) argument
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/external/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp178 unsigned Slot = getSlot(RegNo);
179 return Slot < StackTop && Stack[Slot] == RegNo;
1312 unsigned Slot = getSlot(SrcFP); local
1313 Stack[Slot] = DstFP;
1314 RegMap[DstFP] = Slot;
/external/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp216 const BasicBlock *getIRBlock(unsigned Slot);
217 const BasicBlock *getIRBlock(unsigned Slot, const Function &F);
219 const Value *getIRValue(unsigned Slot);
1830 int Slot = MST.getLocalSlot(&BB); local
1831 if (Slot == -1)
1833 Slots2BasicBlocks.insert(std::make_pair(unsigned(Slot), &BB));
1838 unsigned Slot,
1840 auto BlockInfo = Slots2BasicBlocks.find(Slot);
1846 const BasicBlock *MIParser::getIRBlock(unsigned Slot) { argument
1849 return getIRBlockFromSlot(Slot, Slots2BasicBlock
1837 getIRBlockFromSlot( unsigned Slot, const DenseMap<unsigned, const BasicBlock *> &Slots2BasicBlocks) argument
1852 getIRBlock(unsigned Slot, const Function &F) argument
1862 int Slot = MST.getLocalSlot(V); local
1882 getIRValue(unsigned Slot) argument
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/external/llvm/utils/TableGen/
H A DDAGISelMatcher.h909 unsigned Slot; member in class:llvm::EmitConvertToTargetMatcher
912 : Matcher(EmitConvertToTarget), Slot(slot) {}
914 unsigned getSlot() const { return Slot; }
923 return cast<EmitConvertToTargetMatcher>(M)->Slot == Slot;
925 unsigned getHashImpl() const override { return Slot; }
990 unsigned Slot; member in class:llvm::EmitNodeXFormMatcher
994 : Matcher(EmitNodeXForm), Slot(slot), NodeXForm(nodeXForm) {}
996 unsigned getSlot() const { return Slot; }
1006 return cast<EmitNodeXFormMatcher>(M)->Slot
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