Searched defs:V0 (Results 1 - 25 of 31) sorted by relevance

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/external/opencv3/samples/cpp/tutorial_code/calib3d/real_time_pose_estimation/src/
H A DMesh.cpp17 Triangle::Triangle(int id, cv::Point3f V0, cv::Point3f V1, cv::Point3f V2) argument
19 id_ = id; v0_ = V0; v1_ = V1; v2_ = V2;
H A DPnPProblem.cpp234 cv::Point3f V0 = mesh->getVertex(triangles_list[i][0]); local
238 Triangle T(i, V0, V1, V2);
/external/skia/src/sfnt/
H A DSkOTTable_OS_2.h30 //original V0 TT
32 struct V0 : SkOTTableOS2_V0 { } v0; struct in union:SkOTTableOS2::Version
46 static_assert(sizeof(SkOTTableOS2::Version::V0) == 78, "sizeof_SkOTTableOS2__V0_not_78");
/external/llvm/unittests/Analysis/
H A DScalarEvolutionTest.cpp59 Value *V0 = new GlobalVariable(M, Ty, false, GlobalValue::ExternalLinkage, Init, "V0"); local
65 const SCEV *S0 = SE.getSCEV(V0);
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
91 V1->replaceAllUsesWith(V0);
93 // After the RAUWs, these should all be pointing to V0.
94 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
95 EXPECT_EQ(cast<SCEVUnknown>(M1->getOperand(1))->getValue(), V0);
96 EXPECT_EQ(cast<SCEVUnknown>(M2->getOperand(1))->getValue(), V0);
/external/scrypt/lib/crypto/
H A Dcrypto_scrypt-neon.c197 void * B0, * V0, * XY0; local
236 if ((errno = posix_memalign(&V0, 64, 128 * r * N)) != 0)
238 V = (uint32_t *)(V0);
248 if ((V0 = malloc(128 * r * N + 63)) == NULL)
250 V = (uint32_t *)(((uintptr_t)(V0) + 63) & ~ (uintptr_t)(63));
254 if ((V0 = mmap(NULL, 128 * r * N, PROT_READ | PROT_WRITE,
262 V = (uint32_t *)(V0);
287 if (munmap(V0, 128 * r * N))
290 free(V0);
H A Dcrypto_scrypt-sse.c270 void * B0, * V0, * XY0; local
309 if ((errno = posix_memalign(&V0, 64, 128 * r * N)) != 0)
311 V = (uint32_t *)(V0);
321 if ((V0 = malloc(128 * r * N + 63)) == NULL)
323 V = (uint32_t *)(((uintptr_t)(V0) + 63) & ~ (uintptr_t)(63));
327 if ((V0 = mmap(NULL, 128 * r * N, PROT_READ | PROT_WRITE,
335 V = (uint32_t *)(V0);
360 if (munmap(V0, 128 * r * N))
363 free(V0);
/external/clang/test/CodeGen/
H A Dext-vector.c282 int4 test15(uint4 V0) { argument
284 int4 V = !V0;
/external/fdlibm/
H A De_j1.c147 static const double V0[5] = { variable
149 static double V0[5] = {
208 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4]))));
/external/llvm/lib/Target/Mips/
H A DMips16ISelDAGToDAG.cpp77 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); local
80 V0 = RegInfo.createVirtualRegister(RC);
84 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
H A DMipsSEISelDAGToDAG.cpp140 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); local
145 V0 = RegInfo.createVirtualRegister(RC);
156 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
158 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
170 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
172 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
185 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
187 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
209 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
212 MF.getRegInfo().addLiveIn(Mips::V0);
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp224 SDValue V0 = N->getOperand(i+1); local
226 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp29 static inline unsigned short MakeMask(unsigned V0, unsigned V1, argument
31 return (V0 << (3*4)) | (V1 << (2*4)) | (V2 << (1*4)) | (V3 << (0*4));
/external/webp/src/enc/
H A Dpicture_tools.c146 #define BLEND(V0, V1, ALPHA) \
147 ((((V0) * (255 - (ALPHA)) + (V1) * (ALPHA)) * 0x101) >> 16)
148 #define BLEND_10BIT(V0, V1, ALPHA) \
149 ((((V0) * (1020 - (ALPHA)) + (V1) * (ALPHA)) * 0x101) >> 18)
162 const int V0 = VP8RGBToV(4 * red, 4 * green, 4 * blue, 4 * YUV_HALF); local
188 v[x] = BLEND_10BIT(V0, v[x], alpha);
193 v[x] = BLEND_10BIT(V0, v[x], alpha);
/external/clang/test/Parser/
H A Drecovery.cpp151 enum class EC3 { V0 = 0, V5 = 5 }; // expected-note {{declared here}} member in class:MissingBrace::S::PR17084::TempID::EC3
166 case EC3::V0: break;
H A DMicrosoftExtensions.cpp310 __declspec(property) int V0; // expected-error {{expected '(' after 'property'}} member in struct:pure_virtual_dtor_inline::StructWithProperty
/external/clang/lib/Driver/
H A DToolChains.h485 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0, argument
488 return TargetVersion < VersionTuple(V0, V1, V2);
491 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const { argument
493 return TargetVersion < VersionTuple(V0, V1, V2);
/external/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp199 Value *V0 = I->getOperand(0); local
201 if (isa<ConstantInt>(V0))
202 std::swap(V0, V1);
206 SymbolicPart = V0;
987 Value *V0 = Sub->getOperand(0);
988 if (isReassociableOp(V0, Instruction::Add, Instruction::FAdd) ||
989 isReassociableOp(V0, Instruction::Sub, Instruction::FSub))
/external/webp/src/dsp/
H A Dyuv_sse2.c29 const __m128i* const V0,
44 const __m128i R0 = _mm_mulhi_epu16(*V0, k26149);
49 const __m128i G1 = _mm_mulhi_epu16(*V0, k13320);
84 const __m128i Y0 = Load_HI_16(y), U0 = Load_HI_16(u), V0 = Load_HI_16(v); local
85 ConvertYUV444ToRGB(&Y0, &U0, &V0, R, G, B);
93 const __m128i Y0 = Load_HI_16(y), U0 = Load_UV_HI_8(u), V0 = Load_UV_HI_8(v); local
94 ConvertYUV444ToRGB(&Y0, &U0, &V0, R, G, B);
680 __m128i r0, g0, b0, r1, g1, b1, U0, V0, U1, V1; local
686 ConvertRGBToUV(&r0, &g0, &b0, &U0, &V0);
696 V0
27 ConvertYUV444ToRGB(const __m128i* const Y0, const __m128i* const U0, const __m128i* const V0, __m128i* const R, __m128i* const G, __m128i* const B) argument
739 __m128i r, g, b, U0, V0, U1, V1; local
[all...]
/external/libgdx/extensions/gdx-bullet/jni/src/bullet/LinearMath/
H A DbtVector3.h653 __m128 V0 = _mm_xor_ps(btvMzeroMask, V); local
654 __m128 V2 = _mm_movelh_ps(V0, V);
656 __m128 V1 = _mm_shuffle_ps(V, V0, 0xCE);
658 V0 = _mm_shuffle_ps(V0, V, 0xDB);
661 v0->mVec128 = V0;
/external/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp1530 const Value *V0 = GetLinearExpression(Var0.V, V0Scale, V0Offset, V0ZExtBits, local
1537 V0SExtBits != V1SExtBits || !isValueEqualInPotentialCycles(V0, V1))
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp396 Value *V0 = I->getOperand(0); local
398 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) {
404 Addend0.set(C, V0);
559 Value *V0 = I->getOperand(0); local
561 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) &&
H A DInstCombineCalls.cpp616 Value *V0 = LowInputSelect ? II.getArgOperand(1) : II.getArgOperand(0); local
620 V0 = LowHalfZero ? ZeroVector : V0;
634 return Builder.CreateShuffleVector(V0, V1, ShuffleMask);
/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp261 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
262 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
263 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
264 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
267 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
268 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
269 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1592 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { argument
1593 SDLoc dl(V0.getNode());
1598 const SDValue Ops[] = { RegClass, V0, SubReg
1603 createSRegPairNode(EVT VT, SDValue V0, SDValue V1) argument
1614 createDRegPairNode(EVT VT, SDValue V0, SDValue V1) argument
1625 createQRegPairNode(EVT VT, SDValue V0, SDValue V1) argument
1636 createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1651 createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1666 createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1994 SDValue V0 = N->getOperand(Vec0Idx + 0); local
2047 SDValue V0 = N->getOperand(Vec0Idx + 0); local
2159 SDValue V0 = N->getOperand(Vec0Idx + 0); local
2295 SDValue V0 = N->getOperand(FirstTblReg + 0); local
3335 SDValue V0 = N->getOperand(0); local
3832 SDValue V0 = N->getOperand(i+1); local
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp319 static const MCPhysReg VecLstS[] = { Hexagon::V0, Hexagon::V1,
484 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
489 unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
2139 SDValue V0 = BVN->getOperand(0); local
2142 if (BVN->getOperand(i) != V0)
2235 SDValue V0 = BVN->getOperand(0); local
2238 if (V0.getOpcode() == ISD::UNDEF)
2239 V0 = DAG.getConstant(0, dl, MVT::i32);
2243 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
2248 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp3167 SDValue V0 = GetPromotedInteger(N->getOperand(0)); local
3169 EVT OutVT = V0.getValueType();
3171 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3258 SDValue V0 = GetPromotedInteger(N->getOperand(0)); local
3263 V0, ConvElem, N->getOperand(2));
3268 SDValue V0 = GetPromotedInteger(N->getOperand(0)); local
3272 V0->getValueType(0).getScalarType(), V0, V1);
3282 SDValue V0 = GetPromotedInteger(N->getOperand(0)); local
3283 MVT InVT = V0
[all...]

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