| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.h | 77 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.h | 77 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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| H A D | SIISelLowering.cpp | 476 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, argument
486 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
489 if (Size >= 8 && DstAlign >= 4)
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| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 64 unsigned DstAlign = getKnownAlignment(MI->getArgOperand(0), DL, MI, AC, DT); local
66 unsigned MinAlign = std::min(DstAlign, SrcAlign);
139 DstAlign = std::max(DstAlign, CopyAlign);
148 S->setAlignment(DstAlign);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 310 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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| H A D | AArch64ISelLowering.cpp | 7149 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, argument
7152 (DstAlign == 0 || DstAlign % AlignCheck == 0));
7155 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, argument
7167 (memOpAlign(SrcAlign, DstAlign, 16) ||
7172 (memOpAlign(SrcAlign, DstAlign, 8) ||
7177 (memOpAlign(SrcAlign, DstAlign, 4) ||
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 274 unsigned DstAlign, unsigned SrcAlign,
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| H A D | ARMISelLowering.cpp | 10670 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, argument
10673 (DstAlign == 0 || DstAlign % AlignCheck == 0));
10677 unsigned DstAlign, unsigned SrcAlign,
10688 (memOpAlign(SrcAlign, DstAlign, 16) ||
10692 (memOpAlign(SrcAlign, DstAlign, 8) ||
10676 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const argument
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 551 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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| H A D | MipsISelLowering.cpp | 3612 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, argument
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 612 /// lowering. If DstAlign is zero that means it's safe to destination
622 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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| H A D | PPCISelLowering.cpp | 11391 /// lowering. If DstAlign is zero that means it's safe to destination
11401 unsigned DstAlign, unsigned SrcAlign,
11410 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11418 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11400 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const argument
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 655 /// lowering. If DstAlign is zero that means it's safe to destination
664 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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| H A D | X86ISelLowering.cpp | 1957 /// lowering. If DstAlign is zero that means it's safe to destination
1968 unsigned DstAlign, unsigned SrcAlign,
1977 ((DstAlign == 0 || DstAlign >= 16) &&
1967 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const argument
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| H A D | SROA.cpp | 2848 unsigned DstAlign = SliceAlign;
2851 std::swap(SrcAlign, DstAlign);
2882 IRB.CreateAlignedStore(Src, DstPtr, DstAlign, II.isVolatile()));
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 4158 unsigned DstAlign, unsigned SrcAlign,
4165 assert((SrcAlign == 0 || SrcAlign >= DstAlign) &&
4169 // it's the inferred alignment of the source. 'DstAlign', on the other hand,
4174 EVT VT = TLI.getOptimalMemOpType(Size, DstAlign, SrcAlign,
4180 if (DstAlign >= DAG.getDataLayout().getPointerPrefAlignment(AS) ||
4181 TLI.allowsMisalignedMemoryAccesses(VT, AS, DstAlign)) {
4184 switch (DstAlign & 7) {
4241 TLI.allowsMisalignedMemoryAccesses(VT, AS, DstAlign, &Fast) && Fast)
4156 FindOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit, uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, bool AllowOverlap, SelectionDAG &DAG, const TargetLowering &TLI) argument
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