Searched refs:Op3 (Results 1 - 25 of 25) sorted by relevance

/external/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.h30 SDValue Op3, unsigned Align, bool isVolatile,
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp260 unsigned &Op3) {
270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
539 unsigned Op1, Op2, Op3; local
540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
552 unsigned Op1, Op2, Op3; local
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
565 unsigned Op1, Op2, Op3; local
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3) argument
578 unsigned Op1, Op2, Op3; local
591 unsigned Op1, Op2, Op3; local
605 unsigned Op1, Op2, Op3; local
620 unsigned Op1, Op2, Op3; local
634 unsigned Op1, Op2, Op3; local
648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
682 unsigned Op1, Op2, Op3, Op4, Op5; local
702 unsigned Op1, Op2, Op3; local
721 unsigned Op1, Op2, Op3; local
[all...]
/external/llvm/include/llvm/Target/
H A DTargetSelectionDAGInfo.h52 SDValue Op3, unsigned Align, bool isVolatile,
69 SDValue Op3, unsigned Align, bool isVolatile,
85 SDValue Op3, unsigned Align, bool isVolatile,
98 SDValue Op3, MachinePointerInfo Op1PtrInfo,
49 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
66 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
82 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
95 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h60 SDValue Op3, unsigned Align,
/external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/
H A Dreduce.hpp157 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
162 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
178 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
182 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
/external/opencv3/modules/cudev/include/opencv2/cudev/block/
H A Dreduce.hpp71 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
75 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
80 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp104 MachineOperand &Op3 = MI->getOperand(3); // Modifier value. local
108 Hexagon::C6)->addOperand(Op3);
226 MachineOperand &Op3 = MI->getOperand(3); // Modifier value. local
229 Hexagon::C6)->addOperand(Op3);
H A DHexagonSplitDouble.cpp880 MachineOperand &Op3 = MI->getOperand(3); local
881 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
882 int64_t Sh64 = Op3.getImm();
902 // Op0 = S2_asl_i_p_or Op1, Op2, Op3
903 // means: Op0 = or (Op1, asl(Op2, Op3))
H A DHexagonInstrInfo.cpp959 const MachineOperand &Op3 = MI->getOperand(3); local
963 unsigned Rt = Op3.getReg();
967 unsigned K3 = getKillRegState(Op3.isKill());
/external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/
H A Dreduce.hpp186 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
191 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
207 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
211 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
/external/opencv3/modules/core/include/opencv2/core/cuda/
H A Dreduce.hpp66 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
70 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
75 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
/external/opencv3/modules/cudev/include/opencv2/cudev/warp/
H A Dreduce.hpp69 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
73 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
78 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
/external/opencv3/modules/core/include/opencv2/core/cuda/detail/
H A Dreduce.hpp168 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
173 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
178 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
182 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp69 const MCOperand &Op3 = MI->getOperand(3); local
73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
76 switch (Op3.getImm()) {
109 if (Op2.isImm() && Op3.isImm()) {
113 int64_t imms = Op3.getImm();
143 if (Op2.getImm() > Op3.getImm()) {
146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h920 SDValue Op3);
922 SDValue Op3, SDValue Op4);
924 SDValue Op3, SDValue Op4, SDValue Op5);
936 SDValue Op1, SDValue Op2, SDValue Op3);
951 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
953 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
974 SDValue Op1, SDValue Op2, SDValue Op3);
983 SDValue Op1, SDValue Op2, SDValue Op3);
990 SDValue Op3);
H A DSelectionDAGNodes.h844 const SDValue &Op2, const SDValue &Op3) {
852 Ops[3].setInitial(Op3);
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3787 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local
3788 if (Op2.isReg() && Op3.isImm()) {
3789 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm());
3809 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext()));
3810 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(),
3811 Op3.getEndLoc(), getContext());
3873 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local
3876 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) {
3877 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3
3937 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp5766 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { argument
5767 SDValue Ops[] = { Op1, Op2, Op3 };
5773 SDValue Op3, SDValue Op4) {
5774 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
5780 SDValue Op3, SDValue Op4, SDValue Op5) {
5781 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
5852 SDValue Op2, SDValue Op3) {
5854 SDValue Ops[] = { Op1, Op2, Op3 };
5909 SDValue Op3) {
5911 SDValue Ops[] = { Op1, Op2, Op3 };
5772 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument
5779 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument
5850 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument
5906 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
5915 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
6071 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument
6108 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
6134 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
[all...]
H A DSelectionDAGBuilder.cpp4382 SDValue Op3 = getValue(I.getArgOperand(2));
4388 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4398 SDValue Op3 = getValue(I.getArgOperand(2));
4404 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4412 SDValue Op3 = getValue(I.getArgOperand(2));
4418 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
H A DLegalizeIntegerTypes.cpp231 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); local
236 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
/external/llvm/include/llvm/IR/
H A DPatternMatch.h1253 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument
1254 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
/external/llvm/lib/Analysis/
H A DConstantFolding.cpp1769 if (const ConstantFP *Op3 = dyn_cast<ConstantFP>(Operands[2])) {
1776 Op3->getValueAPF(),
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2988 SDValue Op0, Op1, Op2, Op3, Op4; local
3000 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
3008 OutOps.push_back(Op3);
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5404 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); local
5406 if (!Op3.isReg() || !Op4.isReg())
5409 auto Op3Reg = Op3.getReg();
5923 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); local
5924 if (Op3.isMem()) {
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp175 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
173 fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument

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