Searched refs:SETCC (Results 1 - 25 of 33) sorted by relevance

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/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp863 { ISD::SETCC, MVT::v2f64, 1 },
864 { ISD::SETCC, MVT::v4f32, 1 },
865 { ISD::SETCC, MVT::v2i64, 1 },
866 { ISD::SETCC, MVT::v4i32, 1 },
867 { ISD::SETCC, MVT::v8i16, 1 },
868 { ISD::SETCC, MVT::v16i8, 1 },
872 { ISD::SETCC, MVT::v4f64, 1 },
873 { ISD::SETCC, MVT::v8f32, 1 },
875 { ISD::SETCC, MVT::v4i64, 4 },
876 { ISD::SETCC, MV
[all...]
H A DX86ISelLowering.cpp421 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
424 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
425 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
426 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f128 , Custom);
433 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
736 setOperationAction(ISD::SETCC, VT, Expand);
851 setOperationAction(ISD::SETCC, MV
[all...]
H A DX86ISelLowering.h95 SETCC,
100 // Same as SETCC except it's materialized with a sbb and the value is all
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
718 /// Return the value type to use for ISD::SETCC.
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
H A DR600ISelLowering.cpp48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h52 SETCC,
H A DMSP430ISelLowering.cpp108 setOperationAction(ISD::SETCC, MVT::i8, Custom);
109 setOperationAction(ISD::SETCC, MVT::i16, Custom);
192 case ISD::SETCC: return LowerSETCC(Op, DAG);
1150 case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h369 SETCC, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
301 if (Cond->getOpcode() == ISD::SETCC) {
362 // Turn it into a scalar SETCC.
363 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
403 // Turn it into a scalar SETCC.
404 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
617 case ISD::SETCC:
1402 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1946 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1947 HiRes = DAG.getNode(ISD::SETCC, D
[all...]
H A DLegalizeVectorOps.cpp293 case ISD::SETCC:
718 case ISD::SETCC:
1040 Ops[i] = DAG.getNode(ISD::SETCC, dl,
H A DTargetLowering.cpp122 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
222 ISD::SETCC, dl,
228 ISD::SETCC, dl,
1383 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1489 (isOperationLegal(ISD::SETCC, newVT) &&
1536 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1537 if (N0.getOpcode() == ISD::SETCC &&
1588 Op0.getOperand(0).getOpcode() == ISD::SETCC
[all...]
H A DDAGCombiner.cpp718 if (N.getOpcode() == ISD::SETCC) {
1399 case ISD::SETCC: return visitSETCC(N);
2929 TLI.isOperationLegal(ISD::SETCC, LL.getValueType())))) {
3620 TLI.isOperationLegal(ISD::SETCC, LL.getValueType())))) {
4132 case ISD::SETCC:
4375 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
5037 // can find the SETCC that produced it and inspect its operands. This is
5038 // fairly easy if C is the SETCC node, but it can potentially be
5165 if (N0.getOpcode() == ISD::SETCC) {
5282 // SETCC, the
13806 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0), local
[all...]
H A DLegalizeDAG.cpp1262 case ISD::SETCC:
1265 Node->getOpcode() == ISD::SETCC ? 2 :
1802 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1805 /// If the SETCC has been legalized using AND / OR, then the legalized node
1809 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1813 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1815 /// will be set to true. The caller must invert the result of the SETCC with
3697 if (Tmp1.getOpcode() == ISD::SETCC) {
3746 if (Tmp2.getOpcode() == ISD::SETCC) {
3763 case ISD::SETCC
[all...]
H A DSelectionDAGDumper.cpp212 case ISD::SETCC: return "setcc";
H A DLegalizeIntegerTypes.cpp77 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
614 // Get the SETCC result using the canonical SETCC type.
894 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
936 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
2665 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2699 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2773 Tmp2 = DAG.getNode(ISD::SETCC, dl,
H A DLegalizeFloatTypes.cpp745 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
1494 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1515 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1733 case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
1797 // Construct a SETCC that compares the promoted values and sets the conditional
/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
263 setTargetDAGCombine(ISD::SETCC);
1035 if (Intr->getOpcode() == ISD::SETCC) {
1812 if (LHS.getOpcode() == ISD::SETCC &&
1813 RHS.getOpcode() == ISD::SETCC) {
1992 case ISD::SETCC:
H A DR600ISelLowering.cpp67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
83 setOperationAction(ISD::SETCC, MVT::i32, Expand);
84 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1082 ISD::SETCC,
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1233 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1251 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1257 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1619 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1620 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1806 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
2607 case ISD::SETCC: return LowerSETCC(Op, DAG);
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp79 setTargetDAGCombine(ISD::SETCC);
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
222 setOperationAction(ISD::SETCC, MVT::i64, Legal);
285 setOperationAction(ISD::SETCC, Ty, Legal);
322 setOperationAction(ISD::SETCC, Ty, Legal);
1002 if (Op0->getOpcode() != ISD::SETCC)
1096 case ISD::SETCC:
H A DMipsISelLowering.cpp268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
282 setOperationAction(ISD::SETCC, MVT::f32, Custom);
283 setOperationAction(ISD::SETCC, MVT::f64, Custom);
549 // must be a SETCC node
550 if (Op.getOpcode() != ISD::SETCC)
588 if ((SetCC.getOpcode() != ISD::SETCC) ||
632 // of a SETCC operator is always MVT::i32 for non-vector types.
876 case ISD::SETCC: return lowerSETCC(Op, DAG);
1657 DAG.getNode(ISD::SETCC, DL, getSetCCResultType(DAG.getDataLayout(),
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
165 setOperationAction(ISD::SETCC, MVT::f128, Custom);
275 setOperationAction(ISD::SETCC, MVT::f16, Promote);
345 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
378 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
550 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
672 setOperationAction(ISD::SETCC, V
[all...]
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1592 case ICmp: return ISD::SETCC;
1593 case FCmp: return ISD::SETCC;
/external/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp107 setOperationAction(ISD::SETCC, MVT::i64, Expand);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1543 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1544 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1545 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1546 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1570 setOperationAction(ISD::SETCC, MVT::i64, Expand);

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