Searched refs:SIGN_EXTEND (Results 1 - 25 of 38) sorted by relevance

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/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp561 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
568 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
571 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
611 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
613 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
615 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
617 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
619 { ISD::SIGN_EXTEND, MV
[all...]
H A DX86ISelLowering.cpp748 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
1136 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1137 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1448 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1454 setOperationAction(ISD::SIGN_EXTEND, MV
[all...]
H A DX86FastISel.cpp568 /// ISD::SIGN_EXTEND).
1083 ISD::SIGN_EXTEND;
2310 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::SIGN_EXTEND, InputReg,
2965 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
2989 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
205 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
207 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
209 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
211 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp79 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
81 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
87 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
89 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
91 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
93 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
95 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
224 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
H A DARMISelLowering.cpp618 setTargetDAGCombine(ISD::SIGN_EXTEND);
1637 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
3947 CastOpc = ISD::SIGN_EXTEND;
6207 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
6285 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
6292 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
6434 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6435 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6467 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6468 N1 = DAG.getNode(ISD::SIGN_EXTEND, d
[all...]
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h387 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
389 SIGN_EXTEND, enumerator in enum:llvm::ISD::NodeType
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand);
198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand);
H A DSIISelLowering.cpp424 && Arg0.getOpcode() == ISD::SIGN_EXTEND
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp114 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
195 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
611 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp990 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1401 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1489 case ISD::SIGN_EXTEND:
1769 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1771 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
2502 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2503 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2616 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2617 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2729 N0.getOpcode() == ISD::SIGN_EXTEND ||
[all...]
H A DFunctionLoweringInfo.cpp64 // prefer to use SIGN_EXTEND.
78 ExtendKind = ISD::SIGN_EXTEND;
H A DLegalizeVectorOps.cpp297 case ISD::SIGN_EXTEND:
453 ISD::SIGN_EXTEND;
H A DLegalizeVectorTypes.cpp96 case ISD::SIGN_EXTEND:
438 case ISD::SIGN_EXTEND:
659 case ISD::SIGN_EXTEND:
1445 case ISD::SIGN_EXTEND:
2077 case ISD::SIGN_EXTEND:
2973 case ISD::SIGN_EXTEND:
3060 case ISD::SIGN_EXTEND:
H A DLegalizeIntegerTypes.cpp105 case ISD::SIGN_EXTEND:
348 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
455 if (N->getOpcode() == ISD::SIGN_EXTEND)
895 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1323 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
2338 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
H A DLegalizeFloatTypes.cpp710 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1401 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1409 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1413 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
H A DSelectionDAGDumper.cpp240 case ISD::SIGN_EXTEND: return "sign_extend";
H A DSelectionDAG.cpp235 return ISD::SIGN_EXTEND;
1019 getNode(ISD::SIGN_EXTEND, DL, VT, Op) :
2304 case ISD::SIGN_EXTEND: {
2547 case ISD::SIGN_EXTEND:
2874 case ISD::SIGN_EXTEND:
3032 case ISD::SIGN_EXTEND:
3034 "Invalid SIGN_EXTEND!");
3042 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
3076 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
3102 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
[all...]
H A DFastISel.cpp327 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
1622 return selectCast(I, ISD::SIGN_EXTEND);
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp532 if (IndexOpcode == ISD::SIGN_EXTEND ||
822 case ISD::SIGN_EXTEND: {
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp736 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1229 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1249 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1250 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1255 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1256 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
H A DHexagonISelDAGToDAG.cpp629 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
655 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
1503 case ISD::SIGN_EXTEND:
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1467 ExtendKind = ISD::SIGN_EXTEND;
1581 case SExt: return ISD::SIGN_EXTEND;
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp855 setTargetDAGCombine(ISD::SIGN_EXTEND);
4955 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5526 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5808 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
6457 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6551 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
9512 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9524 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9534 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9565 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
[all...]
/external/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp321 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);

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