Searched refs:SrcVT (Results 1 - 25 of 29) sorted by relevance

12

/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
806 MVT SrcVT = SrcEVT.getSimpleVT();
808 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
821 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
822 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
832 switch (SrcVT.SimpleTy) {
872 if (!PPCEmitIntExt(SrcVT, SrcReg
897 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
915 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
941 PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg, bool IsSigned) argument
1096 MVT DstVT, SrcVT; local
1699 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1770 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp154 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
220 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
224 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
228 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1112 MVT SrcVT = RetVT; local
1139 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1237 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
2728 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
2729 if (SrcVT
2764 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); local
2934 MVT SrcVT = ArgVT; local
2944 MVT SrcVT = ArgVT; local
3901 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4008 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4129 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4211 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool IsZExt) argument
4320 optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT) argument
4377 MVT SrcVT; local
4491 MVT SrcVT = VT; local
4557 MVT SrcVT = RetVT; local
4636 MVT RetVT, SrcVT; local
[all...]
H A DAArch64ISelDAGToDAG.cpp368 EVT SrcVT; local
370 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
372 SrcVT = N.getOperand(0).getValueType();
374 if (!IsLoadStore && SrcVT == MVT::i8)
376 else if (!IsLoadStore && SrcVT == MVT::i16)
378 else if (SrcVT == MVT::i32)
380 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
385 EVT SrcVT = N.getOperand(0).getValueType(); local
386 if (!IsLoadStore && SrcVT == MVT::i8)
388 else if (!IsLoadStore && SrcVT
[all...]
H A DAArch64ISelLowering.cpp3715 EVT SrcVT = In2.getValueType(); local
3717 if (SrcVT.bitsLT(VT))
3719 else if (SrcVT.bitsGT(VT))
4908 EVT SrcVT = Src.ShuffleVec.getValueType(); local
4910 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4915 EVT EltVT = SrcVT.getVectorElementType();
4919 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4920 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4929 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
6584 EVT SrcVT local
8494 EVT SrcVT = Src->getValueType(0); local
9549 EVT SrcVT = N0.getOperand(0).getValueType(); local
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
135 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
939 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
942 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1013 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); local
1016 if (SrcVT !
1141 MVT SrcVT = ArgVT; local
1149 MVT SrcVT = ArgVT; local
1517 EVT SrcVT, DestVT; local
1562 emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1581 emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1596 emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1605 emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1627 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1641 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
[all...]
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp47 /// number in the SrcVT type is expanded to fill the src xmm register and the
49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { argument
58 SrcVT = MVT::v16i8;
63 SrcVT = MVT::v16i8;
70 SrcVT = MVT::v16i8;
75 SrcVT = MVT::v16i8;
82 SrcVT = MVT::v16i8;
87 SrcVT = MVT::v16i8;
95 SrcVT = MVT::v8i16;
100 SrcVT
759 MVT SrcVT, DstVT; local
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp499 EVT SrcVT = LD->getMemoryVT(); local
504 unsigned NumElem = SrcVT.getVectorNumElements();
506 EVT SrcEltVT = SrcVT.getScalarType();
509 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
525 unsigned RemainingBytes = SrcVT.getStoreSize();
617 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
623 SrcVT.getScalarType(),
812 EVT SrcVT = Src.getValueType(); local
813 int NumSrcElements = SrcVT.getVectorNumElements();
827 DAG.getVectorShuffle(SrcVT, D
834 EVT SrcVT = Src.getValueType(); local
859 EVT SrcVT = Src.getValueType(); local
[all...]
H A DFastISel.cpp1244 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
1247 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1257 if (!TLI.isTypeLegal(SrcVT))
1267 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1294 MVT SrcVT = SrcEVT.getSimpleVT();
1303 if (SrcVT == DstVT) {
1304 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1316 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1630 EVT SrcVT local
[all...]
H A DLegalizeDAG.cpp956 EVT SrcVT = LD->getMemoryVT();
957 unsigned SrcWidth = SrcVT.getSizeInBits();
964 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
972 (SrcVT != MVT::i1 ||
977 unsigned NewWidth = SrcVT.getStoreSizeInBits();
982 // way. A zext load from NVT thus automatically gives zext from SrcVT.
999 Result, DAG.getValueType(SrcVT));
1004 DAG.getValueType(SrcVT));
1010 assert(!SrcVT.isVector() && "Unsupported extload!");
1092 SrcVT
[all...]
H A DLegalizeFloatTypes.cpp1392 EVT SrcVT = Src.getValueType(); local
1399 if (SrcVT.bitsLE(MVT::i32)) {
1408 if (SrcVT.bitsLE(MVT::i64)) {
1412 } else if (SrcVT.bitsLE(MVT::i128)) {
1427 SrcVT = Src.getValueType();
1435 switch (SrcVT.getSimpleVT().SimpleTy) {
1454 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT),
H A DLegalizeIntegerTypes.cpp3041 EVT SrcVT = Op.getValueType(); local
3045 // The following optimization is valid only if every value in SrcVT (when
3047 // size of DstVT is >= than the number of bits in SrcVT -1.
3049 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
3050 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
3064 if (SrcVT == MVT::i32)
3066 else if (SrcVT == MVT::i64)
3068 else if (SrcVT == MVT::i128)
3109 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
H A DLegalizeVectorTypes.cpp1214 EVT SrcVT = N->getOperand(0).getValueType(); local
1232 unsigned NumElements = SrcVT.getVectorNumElements();
1234 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1238 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1241 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1244 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
H A DDAGCombiner.cpp5867 EVT SrcVT = N0.getValueType(); local
5908 EVT SplitSrcVT = SrcVT;
6284 EVT SrcVT = N0.getOperand(0).getValueType(); local
6289 if (SrcVT.bitsLT(VT)) {
6290 if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
6301 if (SrcVT.bitsLT(VT)) {
6304 } else if (SrcVT.bitsGT(VT)) {
7083 EVT SrcVT = N0.getValueType(); local
7084 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
7085 TLI.isTruncateFree(SrcVT, V
8963 EVT SrcVT = Src.getValueType(); local
12457 EVT SrcVT = MVT::Other; local
[all...]
/external/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.h102 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT,
H A DX86ShuffleDecode.cpp431 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT, SmallVectorImpl<int> &Mask) { argument
433 unsigned SrcScalarBits = SrcVT.getScalarSizeInBits();
438 assert(SrcVT.getVectorNumElements() >= NumDstElts &&
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1363 MVT SrcVT = SrcEVT.getSimpleVT();
1377 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1378 SrcVT == MVT::i1) {
1392 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1400 switch (SrcVT.SimpleTy) {
1442 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg
2572 EVT SrcVT, DestVT; local
2590 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
[all...]
H A DARMISelLowering.cpp3985 EVT SrcVT = Tmp1.getValueType(); local
4002 if (SrcVT == MVT::f32) {
4036 if (SrcVT == MVT::f64)
4199 EVT SrcVT = Op.getValueType(); local
4201 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4205 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4220 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4222 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
4223 SrcVT.getVectorNumElements() > 1)
4226 DAG.getNode(ARMISD::VREV64, dl, SrcVT, O
5648 EVT SrcVT = Src.ShuffleVec.getValueType(); local
[all...]
/external/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp268 EVT SrcVT = Src.getValueType(); local
274 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
276 SrcVT)),
H A DX86FastISel.cpp96 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
567 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
570 unsigned Src, EVT SrcVT,
572 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1064 EVT SrcVT = TLI.getValueType(DL, RV->getType()); local
1067 if (SrcVT != DstVT) {
1068 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
1076 if (SrcVT
569 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
2181 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
3257 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); local
[all...]
H A DX86ISelLowering.cpp5069 EVT SrcVT = V.getValueType(); local
5072 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
12514 MVT SrcVT = Src.getSimpleValueType();
12518 if (SrcVT.isVector()) {
12519 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12522 DAG.getUNDEF(SrcVT)));
12524 if (SrcVT.getVectorElementType() == MVT::i1) {
12525 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12532 assert(SrcVT <
[all...]
H A DX86ISelDAGToDAG.cpp595 MVT SrcVT = N->getOperand(0).getSimpleValueType(); local
599 if (SrcVT.isVector() || DstVT.isVector())
606 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
627 MemVT = SrcIsSSE ? SrcVT : DstVT;
/external/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp489 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); local
490 if (!DstVT || !SrcVT)
494 unsigned SrcNumElems = SrcVT->getNumElements();
526 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn);
/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1632 EVT SrcVT = Src.getValueType(); local
1638 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1651 !SrcVT.isVector() ||
1652 SrcVT.getVectorElementType() != MVT::i8) {
1660 unsigned NElts = SrcVT.getVectorNumElements();
1661 if (!SrcVT.isSimple() && NElts != 3)
1667 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1668 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
H A DAMDGPUISelDAGToDAG.cpp1231 EVT SrcVT = Src.getValueType(); local
1233 unsigned SrcSize = SrcVT.getSizeInBits();
/external/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp775 EVT SrcVT = TLI.getValueType(DL, CI->getOperand(0)->getType()); local
779 if (SrcVT.isInteger() != DstVT.isInteger())
784 if (SrcVT.bitsLT(DstVT)) return false;
789 if (TLI.getTypeAction(CI->getContext(), SrcVT) ==
791 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT);
797 if (SrcVT != DstVT)

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