Searched refs:StackPtr (Results 1 - 25 of 26) sorted by relevance

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/external/giflib/
H A Dgif_lib_private.h42 StackPtr, /* For character stack (see below). */ member in struct:GifFilePrivateType
H A Ddgif_lib.c773 Private->StackPtr = 0; /* No pixels on the pixel stack. */
795 int j, CrntCode, EOFCode, ClearCode, CrntPrefix, LastCode, StackPtr; local
800 StackPtr = Private->StackPtr;
808 if (StackPtr > LZ_MAX_CODE) {
812 if (StackPtr != 0) {
814 while (StackPtr != 0 && i < LineLen)
815 Line[i++] = Stack[--StackPtr];
857 Stack[StackPtr++] = DGifGetPrefixChar(Prefix,
862 Stack[StackPtr
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/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.h39 /// StackPtr - X86 physical register used as stack ptr.
41 unsigned StackPtr; member in class:llvm::final
132 unsigned getStackRegister() const { return StackPtr; }
H A DX86ExpandPseudo.cpp138 unsigned StackPtr = TRI->getStackRegister(); local
140 TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
H A DX86FrameLowering.cpp49 StackPtr = TRI->getStackRegister();
275 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
276 .addReg(StackPtr)
349 StackPtr),
350 StackPtr, false, Offset);
356 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
357 .addReg(StackPtr)
380 PI->getOperand(0).getReg() == StackPtr){
386 PI->getOperand(0).getReg() == StackPtr) {
1013 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, tru
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H A DX86RegisterInfo.cpp71 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
76 StackPtr = X86::ESP;
553 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
555 BasePtr = StackPtr;
557 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
592 if (BasePtr == StackPtr)
621 return TFI->hasFP(MF) ? FramePtr : StackPtr;
H A DX86FrameLowering.h45 /// instruction operands should be used to manipulate StackPtr and FramePtr.
48 unsigned StackPtr; member in class:llvm::X86FrameLowering
H A DX86CallFrameOptimization.cpp351 unsigned StackPtr = Context.SPCopy->getOperand(0).getReg(); local
380 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
H A DX86ISelLowering.h975 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
H A DX86ISelLowering.cpp2982 SDValue StackPtr, SDValue Arg,
2989 StackPtr, PtrOff);
3175 SDValue StackPtr; local
3246 if (!StackPtr.getNode())
3247 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3249 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3348 if (!StackPtr.getNode())
3349 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3352 StackPtr, Source);
18159 SDValue StackPtr
2981 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp167 SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment); local
168 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
173 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, PtrInfo,
177 Lo = DAG.getLoad(NOutVT, dl, Store, StackPtr, PtrInfo,
182 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
184 StackPtr.getValueType()));
187 Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr,
H A DLegalizeDAG.cpp351 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); local
355 Val, StackPtr, MachinePointerInfo(),
365 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
375 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
387 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
481 SDValue StackPtr = StackBase; local
494 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
499 StackPtr
614 SDValue StackPtr = DAG.CreateStackTemporary(VT); local
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H A DLegalizeVectorTypes.cpp851 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); local
852 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
856 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
863 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
868 StackPtr =
869 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
870 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
873 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
949 SDValue StackPtr local
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H A DLegalizeTypes.cpp931 SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT); local
933 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op, StackPtr,
936 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(),
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp141 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; local
143 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
/external/llvm/lib/CodeGen/
H A DSjLjEHPrepare.cpp419 Value *StackPtr = Builder.CreateConstGEP2_32(doubleUnderJBufTy, JBufPtr, 0, 2, local
423 Builder.CreateStore(Val, StackPtr, /*isVolatile=*/true);
479 Instruction *StoreStackAddr = new StoreInst(StackAddr, StackPtr, true);
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.h499 SDValue &StackPtr,
510 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
H A DARMISelLowering.cpp1510 SDValue StackPtr, SDValue Arg,
1517 StackPtr, PtrOff);
1528 SDValue &StackPtr,
1541 if (!StackPtr.getNode())
1542 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1545 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1616 SDValue StackPtr = local
1659 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1664 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1668 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op
1509 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
1524 PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
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/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.h469 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
488 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
H A DMipsISelLowering.cpp2491 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, argument
2496 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2628 SDValue StackPtr = local
2657 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2732 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3693 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3778 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3690 passByValArg( SDValue Chain, SDLoc DL, std::deque<std::pair<unsigned, SDValue>> &RegsToPass, SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, const CCValAssign &VA) const argument
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp830 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); local
832 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
847 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); local
849 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
884 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); local
886 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
894 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); local
896 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
902 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
925 SDValue StackPtr local
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/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp598 SDValue StackPtr; local
628 if (!StackPtr.getNode())
629 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
632 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4044 SDValue StackPtr; local
4046 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4048 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4049 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4434 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT); local
4437 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4610 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); local
4639 StackPtr, PtrOff);
4677 StackPtr, PtrOff);
4908 SDValue StackPtr local
5476 SDValue StackPtr; local
5853 SDValue StackPtr = DAG.getRegister(SP, PtrVT); local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp713 SDValue StackPtr = local
749 StackPtr.getValueType());
750 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1050 SDValue StackPtr; local
1074 if (!StackPtr.getNode())
1075 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1079 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,

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