/external/llvm/lib/Target/BPF/ |
H A D | BPFTargetMachine.h | 23 BPFSubtarget Subtarget; member in class:llvm::BPFTargetMachine 30 const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; } 32 return &Subtarget;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.cpp | 86 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); local 89 if (Subtarget.hasMips64()) 90 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList 93 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList 97 if (Subtarget.isSingleFloat()) 100 if (Subtarget.isABI_N64()) 103 if (Subtarget.isABI_N32()) 106 if (Subtarget.isFP64bit()) 109 if (Subtarget.isFPXX()) 118 const MipsSubtarget &Subtarget local 152 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); local 284 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); local 307 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); local [all...] |
H A D | MipsTargetMachine.h | 34 MipsSubtarget *Subtarget; member in class:llvm::MipsTargetMachine 50 if (Subtarget) 51 return Subtarget;
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H A D | Mips16ISelDAGToDAG.cpp | 40 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); 41 if (!Subtarget->inMips16Mode()) 75 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); 105 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); 137 AliasReg = Subtarget->getFrameLowering()->hasFP(*MF) 149 AliasReg = Subtarget->getFrameLowering()->hasFP(*MF) 232 if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2()) 234 if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2())
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H A D | MipsSEInstrInfo.cpp | 84 bool isMicroMips = Subtarget.inMicroMipsMode(); 312 if (Subtarget.getABI().ArePtrs64bit()) { 330 bool isMicroMips = Subtarget.inMicroMipsMode(); 430 MipsABIInfo ABI = Subtarget.getABI(); 453 const MipsSubtarget &STI = Subtarget; 502 if (Subtarget.isGP64bit()) 600 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 604 assert(!(Subtarget.isFP64bit() && !Subtarget [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZTargetMachine.h | 27 SystemZSubtarget Subtarget; member in class:llvm::SystemZTargetMachine 36 const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } 38 return &Subtarget;
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreTargetMachine.h | 24 XCoreSubtarget Subtarget; member in class:llvm::XCoreTargetMachine 32 const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; } 34 return &Subtarget;
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430TargetMachine.h | 28 MSP430Subtarget Subtarget; member in class:llvm::MSP430TargetMachine 38 return &Subtarget;
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H A D | MSP430TargetMachine.cpp | 37 Subtarget(TT, CPU, FS, *this) {
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFastISel.cpp | 46 const WebAssemblySubtarget *Subtarget; member in class:__anon12771::final 56 Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
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H A D | WebAssemblyISelDAGToDAG.cpp | 35 const WebAssemblySubtarget *Subtarget; member in class:__anon12772::final 42 : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr), ForCodeSize(false) { 53 Subtarget = &MF.getSubtarget<WebAssemblySubtarget>();
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.h | 25 const HexagonSubtarget *Subtarget; member in class:llvm::HexagonAsmPrinter 32 Subtarget = &Fn.getSubtarget<HexagonSubtarget>();
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUTargetMachine.h | 36 AMDGPUSubtarget Subtarget; member in class:llvm::AMDGPUTargetMachine 45 const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; } 47 return &Subtarget;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUTargetMachine.cpp | 49 Subtarget(TT, CPU, FS), 50 DataLayout(Subtarget.getDataLayout()), 52 Subtarget.device()->getStackAlignment(), 0), 54 InstrItins(&Subtarget.getInstrItineraryData()), 59 if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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H A D | AMDGPUTargetMachine.h | 31 AMDGPUSubtarget Subtarget; member in class:llvm::AMDGPUTargetMachine 54 virtual const AMDGPUSubtarget *getSubtargetImpl() const {return &Subtarget; }
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.cpp | 57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); local 68 if (!Subtarget.is64Bit()) 83 if (ReserveAppRegisters || !Subtarget.is64Bit()) 91 if (!Subtarget.isV9()) { 104 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); local 105 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 174 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); local 183 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { 185 const TargetInstrInfo &TII = *Subtarget [all...] |
H A D | SparcTargetMachine.h | 25 SparcSubtarget Subtarget; member in class:llvm::SparcTargetMachine 34 return &Subtarget;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); local 105 if (Subtarget.hasVSX()) 107 if (Subtarget.hasAltivec()) 112 if (Subtarget.isDarwinABI()) 114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList 116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList 123 ? (Subtarget.hasAltivec() 127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList 134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 136 if (Subtarget 167 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 293 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 329 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 443 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 469 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 514 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 557 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 601 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 651 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 677 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 699 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 759 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 903 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local 990 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); local [all...] |
H A D | PPCFrameLowering.cpp | 87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), 88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), 89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), 90 LinkageSize(computeLinkageSize(Subtarget)), 96 if (Subtarget.isDarwinABI()) { 98 if (Subtarget.isPPC64()) { 108 if (!Subtarget.isSVR4ABI()) { 238 if (Subtarget.isPPC64()) { 439 static_cast<const PPCRegisterInfo *>(Subtarget [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetMachine.h | 31 NVPTXSubtarget Subtarget; member in class:llvm::NVPTXTargetMachine 44 return &Subtarget; 46 const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
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/external/llvm/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 52 const X86Subtarget &Subtarget = local 70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) { 75 V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) { 125 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 154 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, 157 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, 204 const X86Subtarget &Subtarget = local 209 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) 240 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32; 248 Chain = DAG.getCopyToReg(Chain, dl, Subtarget [all...] |
H A D | X86ISelLowering.cpp | 73 : TargetLowering(TM), Subtarget(&STI) { 74 X86ScalarSSEf64 = Subtarget->hasSSE2(); 75 X86ScalarSSEf32 = Subtarget->hasSSE1(); 88 if (Subtarget->isAtom()) 90 else if (Subtarget->is64Bit()) 94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo(); 99 if (Subtarget->hasSlowDivide32()) 101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit()) 105 if (Subtarget 2561 const X86Subtarget& Subtarget = local 2602 get64BitArgumentGPRs(CallingConv::ID CallConv, const X86Subtarget *Subtarget) argument 2620 get64BitArgumentXMMs(MachineFunction &MF, CallingConv::ID CallConv, const X86Subtarget *Subtarget) argument 4542 const X86Subtarget &Subtarget = local 4666 getOnesVector(EVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG, SDLoc dl) argument 4720 getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument 5087 LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget* Subtarget, const TargetLowering &TLI) argument 5157 LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget* Subtarget, const TargetLowering &TLI) argument 5188 LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI) argument 5501 LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget, SelectionDAG &DAG) argument 6032 LowerToAddSub(const BuildVectorSDNode *BV, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument 6134 LowerToHorizontalOp(const BuildVectorSDNode *BV, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument [all...] |
H A D | X86TargetMachine.h | 27 X86Subtarget Subtarget; member in class:llvm::final
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H A D | X86FastISel.cpp | 49 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 51 const X86Subtarget *Subtarget; member in class:__anon12808::final 64 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>(); 65 X86ScalarSSEf64 = Subtarget->hasSSE2(); 66 X86ScalarSSEf32 = Subtarget->hasSSE1(); 136 return Subtarget->getInstrInfo(); 375 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; 384 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; 396 Opc = Subtarget->hasAVX() ? X86::VMOVAPSrm : X86::MOVAPSrm; 398 Opc = Subtarget 1158 X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) argument 2810 computeBytesPoppedByCallee(const X86Subtarget *Subtarget, CallingConv::ID CC, ImmutableCallSite *CS) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 164 : TargetLowering(TM), Subtarget(&STI) { 165 RegInfo = Subtarget->getRegisterInfo(); 166 Itins = Subtarget->getInstrItineraryData(); 170 if (Subtarget->isTargetMachO()) { 172 if (Subtarget->isThumb() && Subtarget->hasVFP2() && 173 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) { 243 if (Subtarget->isTargetWatchOS()) { 255 if (Subtarget 2863 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 2895 LowerPREFETCH(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 3676 canChangeToInt(SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget) argument 6797 ReplaceREADCYCLECOUNTER(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 8143 attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget, MachineInstr *MI, const SDNode *Node) argument 8378 AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8476 AddCombineTo64bitMLAL(SDNode *AddcNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8614 PerformADDCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8626 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8645 PerformADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8691 PerformVMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8722 PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8806 PerformANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8850 PerformORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 9047 PerformXORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 9201 PerformVMOVRRDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 9277 PerformBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 9981 PerformVCVTCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 10037 PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget) argument 10794 isLegalT2AddressImmediate(int64_t V, EVT VT, const ARMSubtarget *Subtarget) argument 10827 isLegalAddressImmediate(int64_t V, EVT VT, const ARMSubtarget *Subtarget) argument [all...] |