| /external/clang/test/CodeGen/ |
| H A D | ppc64-vector.c | 3 typedef short v2i16 __attribute__((vector_size (4))); typedef
13 v2i16 test_v2i16(v2i16 x)
|
| H A D | builtins-mips.c | 12 typedef short v2i16 __attribute__ ((vector_size(4))); typedef
17 v2i16 v2i16_r, v2i16_a, v2i16_b, v2i16_c;
352 v2i16_a = (v2i16) {0xffff, 0x2468};
353 v2i16_b = (v2i16) {0x1234, 0x1111};
356 v2i16_a = (v2i16) {0xffff, 0x2468};
357 v2i16_b = (v2i16) {0x1234, 0x1111};
392 v2i16_b = (v2i16) {0xffff, 0x1555};
393 v2i16_c = (v2i16) {0x1234, 0x3322};
397 v2i16_b = (v2i16) {0xffff, 0x1555};
398 v2i16_c = (v2i16) {
[all...] |
| H A D | systemz-abi-vector.c | 16 typedef __attribute__((vector_size(4))) short v2i16; typedef
70 v2i16 pass_v2i16(v2i16 arg) { return arg; }
|
| H A D | x86_32-arguments-darwin.c | 217 typedef unsigned short v2i16 __attribute__((__vector_size__(4))); typedef
221 v2i16 f54(v2i16 arg) { return arg+arg; }
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
227 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
248 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
251 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
268 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
279 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
282 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
|
| H A D | AArch64ISelLowering.cpp | 429 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
594 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
2028 case MVT::v2i16:
7898 // (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
7899 // (v2i16 (truncate (v2i64)))))
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineValueType.h | 79 v2i16 = 31, // 2 x i16 enumerator in enum:llvm::MVT::SimpleValueType
227 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 ||
328 case v2i16:
406 case v2i16:
456 case v2i16:
608 if (NumElements == 2) return MVT::v2i16;
|
| /external/llvm/lib/IR/ |
| H A D | ValueTypes.cpp | 158 case MVT::v2i16: return "v2i16";
236 case MVT::v2i16: return VectorType::get(Type::getInt16Ty(Context), 2);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 108 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
109 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
140 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
141 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
|
| H A D | ARMISelLowering.cpp | 631 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
6234 case MVT::v2i16:
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 59 (int)MVT::v2i16,
87 (int)MVT::v2i16,
209 setOperationAction(ISD::UDIV, MVT::v2i16, Expand);
666 if (OVT == MVT::v2i16) {
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 239 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
403 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
1227 if (LHSVT == MVT::v2i16) {
1271 if (OpVT == MVT::v2i16) {
1275 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1553 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1735 promoteLdStType(MVT::v2i16, MVT::i32);
1789 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
1806 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1807 setOperationAction(ISD::VSELECT, MVT::v2i16, Custo
[all...] |
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 91 case MVT::v2i16: return "MVT::v2i16";
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
84 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
878 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
935 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
947 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
954 bool IsV216 = (Ty == MVT::v2i16);
974 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
1026 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
|
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 135 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
197 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
198 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
199 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
|
| H A D | R600ISelLowering.cpp | 116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
|
| H A D | SIISelLowering.cpp | 121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 65 case MVT::v2i16:
1914 case MVT::v2i16:
4291 case MVT::v2i16:
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 598 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 },
|
| H A D | X86ISelLowering.cpp | 893 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1397 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 647 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
|