/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 74 int NewOpcode = 0; local 77 NewOpcode = Hexagon::J2_jumpf; 81 NewOpcode = Hexagon::J2_jumpt; 85 NewOpcode = Hexagon::J2_jumpfnewpt; 89 NewOpcode = Hexagon::J2_jumptnewpt; 96 MI->setDesc(TII->get(NewOpcode));
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H A D | HexagonVLIWPacketizer.cpp | 416 int NewOpcode; local 418 NewOpcode = HII->getDotNewPredOp(MI, MBPI); 420 NewOpcode = HII->getDotNewOp(MI); 421 MI->setDesc(HII->get(NewOpcode)); 426 int NewOpcode = HII->getDotOldOp(MI->getOpcode()); local 427 MI->setDesc(HII->get(NewOpcode)); 762 int NewOpcode = HII->getDotNewOp(MI); local 763 const MCInstrDesc &D = HII->get(NewOpcode);
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H A D | HexagonInstrInfo.cpp | 1017 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode); local 1018 Cond[0].setImm(NewOpcode); 3135 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); local 3136 if (NewOpcode >= 0) // Valid predicate new instruction 3137 return NewOpcode; 3765 unsigned NewOpcode = getInvertedPredicatedOpcode(MI->getOpcode()); local 3774 NewOpcode = reversePrediction(NewOpcode); 3776 MI->setDesc(get(NewOpcode));
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 438 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); local 442 if (!NewOpcode) { 447 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); 448 assert(NewOpcode && "No restore instruction available"); 451 MBBI->setDesc(ZII->get(NewOpcode));
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H A D | SystemZInstrInfo.cpp | 49 // each having the opcode given by NewOpcode. 51 unsigned NewOpcode) const { 78 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); 79 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); 96 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); local 97 assert(NewOpcode && "No support for huge argument lists yet"); 98 MI->setDesc(get(NewOpcode)); 731 unsigned NewOpcode; local 733 NewOpcode = SystemZ::RISBG; 736 NewOpcode [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 264 int NewOpcode; local 268 NewOpcode = isINC ? X86::INC16r : X86::DEC16r; 272 NewOpcode = isINC ? X86::INC32r : X86::DEC32r; 275 NewOpcode = isINC ? X86::INC64r : X86::DEC64r; 280 BuildMI(*MFI, I, MI->getDebugLoc(), TII->get(NewOpcode))
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H A D | X86MCInstLower.cpp | 322 unsigned NewOpcode = 0; local 329 NewOpcode = X86::CBW; 333 NewOpcode = X86::CWDE; 337 NewOpcode = X86::CDQE; 341 if (NewOpcode != 0) { 343 Inst.setOpcode(NewOpcode);
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H A D | X86InstrInfo.cpp | 4924 unsigned NewOpcode = 0; local 4947 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 4948 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 4949 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 4950 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 4951 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 4952 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 4953 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 4954 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 4955 case X86::SUB64ri32: NewOpcode [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 138 int NewOpcode; local 140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; 141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; 147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; 154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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/external/llvm/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 513 unsigned NewOpcode = local 517 const MCInstrDesc &NewDesc = TII->get(NewOpcode);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 881 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; local 882 MI.setDesc(TII.get(NewOpcode));
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H A D | PPCAsmPrinter.cpp | 980 unsigned NewOpcode = local 984 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) 994 unsigned NewOpcode = local 1000 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode)
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H A D | PPCISelDAGToDAG.cpp | 4118 unsigned NewOpcode; local 4122 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; 4123 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; 4124 case PPC::SLW: NewOpcode = PPC::SLW8; break; 4125 case PPC::SRW: NewOpcode = PPC::SRW8; break; 4126 case PPC::LI: NewOpcode = PPC::LI8; break; 4127 case PPC::LIS: NewOpcode = PPC::LIS8; break; 4128 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; 4129 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; 4130 case PPC::CNTLZW: NewOpcode [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDILCFGStructurizer.cpp | 231 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, 233 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, 235 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode); 236 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode, 239 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, 241 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum); 472 int NewOpcode, DebugLoc DL) { 474 ->CreateMachineInstr(TII->get(NewOpcode), DL); 481 int NewOpcode, DebugLoc DL) { 483 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), D 471 insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL) argument 480 insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL) argument 492 insertInstrBefore( MachineBasicBlock::iterator I, int NewOpcode) argument 504 insertCondBranchBefore( MachineBasicBlock::iterator I, int NewOpcode, DebugLoc DL) argument 517 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, DebugLoc DL) argument 528 insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum) argument [all...] |
H A D | SIISelLowering.cpp | 2356 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet); local 2357 MI->setDesc(TII->get(NewOpcode));
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 1634 std::string NewOpcode; local 1637 NewOpcode = Name; 1638 NewOpcode += '+'; 1639 Name = NewOpcode; 1643 NewOpcode = Name; 1644 NewOpcode += '-'; 1645 Name = NewOpcode; 1651 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1659 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 2633 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; local 2647 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6; 2649 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; 2652 Inst.setOpcode(NewOpcode);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 4158 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local 4162 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); 4170 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local 4174 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
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