/art/disassembler/ |
H A D | disassembler_mips.cc | 414 uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type. local 493 args << StringPrintf("%+d(r%d)", offset, rs); 496 case 'O': // +x(rs) 499 args << StringPrintf("%+d(r%d)", offset, rs); 500 if (rs == 17) { 522 args << offset << " ; move r" << rs << ", "; local 526 case 'S': args << 'r' << rs; break; local 527 case 's': args << 'f' << rs; break; local 549 if (((op == 0x36 && rs == 0 && rt != 0) || // jic 550 (op == 0x19 && rs [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_arm.h | 146 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), argument 147 rs_(rs),
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H A D | assembler_arm32.cc | 167 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. 174 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 181 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 188 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 195 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 813 Register rm, Register rs) { 817 CHECK_NE(rs, kNoRegister); 823 (static_cast<int32_t>(rs) << kRsShift) | 811 EmitMulOp(Condition cond, int32_t opcode, Register rd, Register rn, Register rm, Register rs) argument
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/art/compiler/utils/mips/ |
H A D | assembler_mips.cc | 125 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument 126 CHECK_NE(rs, kNoRegister); 130 static_cast<uint32_t>(rs) << kRsShift | 138 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument 139 CHECK_NE(rs, kNoRegister); 142 static_cast<uint32_t>(rs) << kRsShift | 148 void MipsAssembler::EmitI21(int opcode, Register rs, uint32_t imm21) { argument 149 CHECK_NE(rs, kNoRegister); 152 static_cast<uint32_t>(rs) << kRsShift | 186 void MipsAssembler::Addu(Register rd, Register rs, Registe argument 190 Addiu(Register rt, Register rs, uint16_t imm16) argument 194 Subu(Register rd, Register rs, Register rt) argument 198 MultR2(Register rs, Register rt) argument 203 MultuR2(Register rs, Register rt) argument 208 DivR2(Register rs, Register rt) argument 213 DivuR2(Register rs, Register rt) argument 218 MulR2(Register rd, Register rs, Register rt) argument 223 DivR2(Register rd, Register rs, Register rt) argument 229 ModR2(Register rd, Register rs, Register rt) argument 235 DivuR2(Register rd, Register rs, Register rt) argument 241 ModuR2(Register rd, Register rs, Register rt) argument 247 MulR6(Register rd, Register rs, Register rt) argument 252 MuhR6(Register rd, Register rs, Register rt) argument 257 MuhuR6(Register rd, Register rs, Register rt) argument 262 DivR6(Register rd, Register rs, Register rt) argument 267 ModR6(Register rd, Register rs, Register rt) argument 272 DivuR6(Register rd, Register rs, Register rt) argument 277 ModuR6(Register rd, Register rs, Register rt) argument 282 And(Register rd, Register rs, Register rt) argument 286 Andi(Register rt, Register rs, uint16_t imm16) argument 290 Or(Register rd, Register rs, Register rt) argument 294 Ori(Register rt, Register rs, uint16_t imm16) argument 298 Xor(Register rd, Register rs, Register rt) argument 302 Xori(Register rt, Register rs, uint16_t imm16) argument 306 Nor(Register rd, Register rs, Register rt) argument 310 Movz(Register rd, Register rs, Register rt) argument 315 Movn(Register rd, Register rs, Register rt) argument 320 Seleqz(Register rd, Register rs, Register rt) argument 325 Selnez(Register rd, Register rs, Register rt) argument 330 ClzR6(Register rd, Register rs) argument 335 ClzR2(Register rd, Register rs) argument 340 CloR6(Register rd, Register rs) argument 345 CloR2(Register rd, Register rs) argument 387 Sllv(Register rd, Register rt, Register rs) argument 391 Srlv(Register rd, Register rt, Register rs) argument 395 Rotrv(Register rd, Register rt, Register rs) argument 399 Srav(Register rd, Register rt, Register rs) argument 417 Lb(Register rt, Register rs, uint16_t imm16) argument 421 Lh(Register rt, Register rs, uint16_t imm16) argument 425 Lw(Register rt, Register rs, uint16_t imm16) argument 429 Lwl(Register rt, Register rs, uint16_t imm16) argument 434 Lwr(Register rt, Register rs, uint16_t imm16) argument 439 Lbu(Register rt, Register rs, uint16_t imm16) argument 443 Lhu(Register rt, Register rs, uint16_t imm16) argument 466 Sb(Register rt, Register rs, uint16_t imm16) argument 470 Sh(Register rt, Register rs, uint16_t imm16) argument 474 Sw(Register rt, Register rs, uint16_t imm16) argument 478 Swl(Register rt, Register rs, uint16_t imm16) argument 483 Swr(Register rt, Register rs, uint16_t imm16) argument 510 Slt(Register rd, Register rs, Register rt) argument 514 Sltu(Register rd, Register rs, Register rt) argument 518 Slti(Register rt, Register rs, uint16_t imm16) argument 522 Sltiu(Register rt, Register rs, uint16_t imm16) argument 530 Beq(Register rs, Register rt, uint16_t imm16) argument 534 Bne(Register rs, Register rt, uint16_t imm16) argument 590 Jalr(Register rd, Register rs) argument 594 Jalr(Register rs) argument 598 Jr(Register rs) argument 606 Auipc(Register rs, uint16_t imm16) argument 611 Addiupc(Register rs, uint32_t imm19) argument 632 Bltc(Register rs, Register rt, uint16_t imm16) argument 652 Bgec(Register rs, Register rt, uint16_t imm16) argument 672 Bltuc(Register rs, Register rt, uint16_t imm16) argument 680 Bgeuc(Register rs, Register rt, uint16_t imm16) argument 688 Beqc(Register rs, Register rt, uint16_t imm16) argument 696 Bnec(Register rs, Register rt, uint16_t imm16) argument 704 Beqzc(Register rs, uint32_t imm21) argument 710 Bnezc(Register rs, uint32_t imm21) argument 726 EmitBcondR2(BranchCondition cond, Register rs, Register rt, uint16_t imm16) argument 780 EmitBcondR6(BranchCondition cond, Register rs, Register rt, uint32_t imm16_21) argument 1148 Movf(Register rd, Register rs, int cc) argument 1154 Movt(Register rd, Register rs, int cc) argument 1306 Lwc1(FRegister ft, Register rs, uint16_t imm16) argument 1310 Ldc1(FRegister ft, Register rs, uint16_t imm16) argument 1314 Swc1(FRegister ft, Register rs, uint16_t imm16) argument 1318 Sdc1(FRegister ft, Register rs, uint16_t imm16) argument 1331 Move(Register rd, Register rs) argument 1339 Not(Register rd, Register rs) argument 1343 Push(Register rs) argument 1459 Addiu32(Register rt, Register rs, int32_t value, Register temp) argument 2163 Beq(Register rs, Register rt, MipsLabel* label) argument 2167 Bne(Register rs, Register rt, MipsLabel* label) argument 2195 Blt(Register rs, Register rt, MipsLabel* label) argument 2205 Bge(Register rs, Register rt, MipsLabel* label) argument 2217 Bltu(Register rs, Register rt, MipsLabel* label) argument 2227 Bgeu(Register rs, Register rt, MipsLabel* label) argument [all...] |
/art/compiler/utils/mips64/ |
H A D | assembler_mips64.cc | 91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, argument 93 CHECK_NE(rs, kNoGpuRegister); 97 static_cast<uint32_t>(rs) << kRsShift | 105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, argument 107 CHECK_NE(rs, kNoGpuRegister); 110 static_cast<uint32_t>(rs) << kRsShift | 131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { argument 132 CHECK_NE(rs, kNoGpuRegister); 135 static_cast<uint32_t>(rs) << kRsShift | 141 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_ argument 179 Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 183 Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 187 Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 191 Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 195 Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 199 Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 203 MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 207 MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 211 DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 215 ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 219 DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 223 ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 227 Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 231 Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 235 Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 239 Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 243 Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 247 Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 251 And(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 255 Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 259 Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 263 Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 267 Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 271 Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 275 Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 303 Dext(GpuRegister rt, GpuRegister rs, int pos, int size) argument 309 Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) argument 356 Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 360 Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 364 Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 368 Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 404 Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 408 Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 412 Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 416 Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 420 Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 424 Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 428 Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 432 Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 436 Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 440 Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 444 Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 452 Dahi(GpuRegister rs, uint16_t imm16) argument 456 Dati(GpuRegister rs, uint16_t imm16) argument 465 Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 469 Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 473 Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 477 Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 481 Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 485 Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 489 Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 493 Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 497 Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 501 Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 505 Clz(GpuRegister rd, GpuRegister rs) argument 509 Clo(GpuRegister rd, GpuRegister rs) argument 513 Dclz(GpuRegister rd, GpuRegister rs) argument 517 Dclo(GpuRegister rd, GpuRegister rs) argument 521 Jalr(GpuRegister rd, GpuRegister rs) argument 525 Jalr(GpuRegister rs) argument 529 Jr(GpuRegister rs) argument 533 Auipc(GpuRegister rs, uint16_t imm16) argument 537 Addiupc(GpuRegister rs, uint32_t imm19) argument 554 Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 571 Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 588 Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 595 Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 602 Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 609 Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 616 Beqzc(GpuRegister rs, uint32_t imm21) argument 621 Bnezc(GpuRegister rs, uint32_t imm21) argument 634 EmitBcondc(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint32_t imm16_21) argument 997 Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) argument 1001 Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) argument 1005 Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) argument 1009 Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) argument 1023 Move(GpuRegister rd, GpuRegister rs) argument 1031 Not(GpuRegister rd, GpuRegister rs) argument 1161 Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) argument 1747 Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument 1759 Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument 1771 Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument 1775 Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument 1779 Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument 1783 Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label) argument 1787 Beqzc(GpuRegister rs, Mips64Label* label) argument 1791 Bnezc(GpuRegister rs, Mips64Label* label) argument [all...] |