| /art/runtime/interpreter/mterp/mips64/ |
| H A D | header.S | 157 sll AT, \reg, 7
158 daddu AT, rIBASE, AT
159 jic AT, 0
172 dlsa AT, \vreg, rFP, 2
173 lw \reg, 0(AT)
178 dlsa AT, \vreg, rFP, 2
179 lwu \reg, 0(AT)
184 dlsa AT, \vreg, rFP, 2
185 lwc1 \reg, 0(AT)
[all...] |
| /art/runtime/interpreter/mterp/mips/ |
| H A D | header.S | 76 #define AT $$at /* assembler temp */ define
275 #define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \
276 .set noat; l.s rd, (AT); .set at
279 sll AT, rix, 2; \
280 addu t8, rFP, AT; \
282 addu t8, rREFS, AT; \
287 sll AT, rix, 2; \
288 addu t8, rFP, AT; \
291 addu t8, rREFS, AT; \
298 sll AT, ri
[all...] |
| /art/compiler/optimizing/ |
| H A D | intrinsics_mips.cc | 285 __ LoadConst32(AT, 0x00FF00FF);
286 __ And(TMP, out, AT);
289 __ And(out, out, AT);
296 __ LoadConst32(AT, 0x0F0F0F0F);
297 __ And(TMP, out, AT);
300 __ And(out, out, AT);
302 __ LoadConst32(AT, 0x33333333);
303 __ And(TMP, out, AT);
306 __ And(out, out, AT);
308 __ LoadConst32(AT,
[all...] |
| H A D | intrinsics_mips64.cc | 430 __ Dsra32(AT, in, 31);
431 __ Xor(out, in, AT);
432 __ Dsubu(out, out, AT);
434 __ Sra(AT, in, 31);
435 __ Xor(out, in, AT);
436 __ Subu(out, out, AT);
608 __ Slt(AT, rhs, lhs);
610 __ Seleqz(out, lhs, AT);
611 __ Selnez(AT, rhs, AT);
[all...] |
| H A D | code_generator_mips.cc | 595 __ MoveFromFpuHigh(AT, f1);
599 __ Move(r2_h, AT);
979 Register card = AT;
1004 // AT and TMP(T8) are used as temporary/scratch registers
1005 // (similar to how AT is used by MIPS assemblers).
1006 blocked_core_registers_[AT] = true;
1099 __ LoadConst32(AT, mirror::Class::kStatusInitialized);
1100 __ Blt(TMP, AT, slow_path->GetEntryLabel());
1349 __ Sltiu(AT, dst_low, low);
1354 __ Sltu(AT, dst_lo
[all...] |
| H A D | code_generator_mips64.cc | 680 GpuRegister gpr = AT;
877 GpuRegister card = AT;
903 // AT, TMP(T8) and TMP2(T3) are used as temporary/scratch
904 // registers (similar to how AT is used by MIPS assemblers).
905 blocked_core_registers_[AT] = true;
982 __ LoadConst32(AT, mirror::Class::kStatusInitialized);
983 __ Bltc(TMP, AT, slow_path->GetEntryLabel());
1715 rhs = AT;
1721 rhs = AT;
2018 __ Sra(AT, TM
[all...] |
| /art/runtime/arch/mips/ |
| H A D | registers_mips.h | 31 AT = 1, // Assembler temporary. enumerator in enum:art::mips::Register
63 TMP = T8, // scratch register (in addition to AT)
|
| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.h | 31 AT = 1, // Assembler temporary. enumerator in enum:art::mips64::GpuRegister
63 TMP = T8, // scratch register (in addition to AT)
64 TMP2 = T3, // scratch register (in addition to AT, reserved for assembler)
|
| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 1389 CHECK_NE(temp, AT); // Must not use AT as temp, as not to overwrite the loaded value.
1390 LoadConst32(AT, offset);
1391 Addu(AT, AT, base);
1392 base = AT;
1409 CHECK_NE(temp, AT); // Must not use AT as temp, as not to overwrite the loaded value.
1410 LoadConst32(AT, offset);
1411 Addu(AT, A
[all...] |
| H A D | assembler_mips_test.cc | 58 registers_.push_back(new mips::Register(mips::AT));
91 secondary_register_names_.emplace(mips::Register(mips::AT), "at");
|
| H A D | assembler_mips.h | 362 void Addiu32(Register rt, Register rs, int32_t value, Register rtmp = AT);
|
| /art/compiler/jni/quick/mips64/ |
| H A D | calling_convention_mips64.cc | 148 return Mips64ManagedRegister::FromGpuRegister(AT);
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 1287 CHECK_NE(indirect_reg, AT);
1717 Auipc(AT, High16Bits(offset));
1718 Jic(AT, Low16Bits(offset));
1724 Auipc(AT, High16Bits(offset));
1725 Jic(AT, Low16Bits(offset));
1808 LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1));
1809 Daddu(AT, AT, base);
1810 base = AT;
1853 LoadConst32(AT, offse
[all...] |
| H A D | assembler_mips64_test.cc | 82 registers_.push_back(new mips64::GpuRegister(mips64::AT));
115 secondary_register_names_.emplace(mips64::GpuRegister(mips64::AT), "at");
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| H A D | assembler_mips64.h | 327 void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT); // MIPS64
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| /art/runtime/interpreter/mterp/out/ |
| H A D | mterp_mips.S | 83 #define AT $at /* assembler temp */ define
282 #define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \
283 .set noat; l.s rd, (AT); .set at
286 sll AT, rix, 2; \
287 addu t8, rFP, AT; \
289 addu t8, rREFS, AT; \
294 sll AT, rix, 2; \
295 addu t8, rFP, AT; \
298 addu t8, rREFS, AT; \
305 sll AT, ri
[all...] |
| H A D | mterp_mips64.S | 164 sll AT, \reg, 7
165 daddu AT, rIBASE, AT
166 jic AT, 0
179 dlsa AT, \vreg, rFP, 2
180 lw \reg, 0(AT)
185 dlsa AT, \vreg, rFP, 2
186 lwu \reg, 0(AT)
191 dlsa AT, \vreg, rFP, 2
192 lwc1 \reg, 0(AT)
[all...] |
| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 182 return MipsManagedRegister::FromCoreRegister(AT);
|