Searched refs:GpuRegister (Results 1 - 10 of 10) sorted by relevance
/art/compiler/utils/mips64/ |
H A D | assembler_mips64.h | 122 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt); 123 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); 124 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 125 void Daddiu(GpuRegister rt, GpuRegister r [all...] |
H A D | assembler_mips64.cc | 91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, 105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, 118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, 131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { 141 void Mips64Assembler::EmitI21(int opcode, GpuRegister r [all...] |
H A D | managed_register_mips64.h | 42 GpuRegister AsGpuRegister() const { 44 return static_cast<GpuRegister>(id_); 70 static Mips64ManagedRegister FromGpuRegister(GpuRegister r) {
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H A D | assembler_mips64_test.cc | 32 bool operator()(const mips64::GpuRegister& a, const mips64::GpuRegister& b) const { 38 mips64::GpuRegister, 43 mips64::GpuRegister, 81 registers_.push_back(new mips64::GpuRegister(mips64::ZERO)); 82 registers_.push_back(new mips64::GpuRegister(mips64::AT)); 83 registers_.push_back(new mips64::GpuRegister(mips64::V0)); 84 registers_.push_back(new mips64::GpuRegister(mips64::V1)); 85 registers_.push_back(new mips64::GpuRegister(mips64::A0)); 86 registers_.push_back(new mips64::GpuRegister(mips6 [all...] |
/art/compiler/optimizing/ |
H A D | intrinsics_mips64.cc | 59 GpuRegister trg_reg = trg.AsRegister<GpuRegister>(); 151 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); 187 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>(); 226 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>(); 227 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); [all...] |
H A D | code_generator_mips64.cc | 38 static constexpr GpuRegister kMethodRegisterArgument = A0; 476 __ Ld(GpuRegister(reg), SP, 0); 483 __ Sd(GpuRegister(reg), SP, 0); 496 GpuRegister(ensure_scratch.GetRegister()), 504 GpuRegister(ensure_scratch.GetRegister()), 510 static dwarf::Reg DWARFReg(GpuRegister reg) { 553 GpuRegister reg = kCoreCalleeSaves[i]; 608 GpuRegister reg = kCoreCalleeSaves[i]; 674 destination.AsRegister<GpuRegister>(), 680 GpuRegister gp [all...] |
H A D | code_generator_mips64.h | 32 static constexpr GpuRegister kParameterCoreRegisters[] = 43 static constexpr GpuRegister kRuntimeParameterCoreRegisters[] = 54 static constexpr GpuRegister kCoreCalleeSaves[] = 62 class InvokeDexCallingConvention : public CallingConvention<GpuRegister, FpuRegister> { 90 class InvokeRuntimeCallingConvention : public CallingConvention<GpuRegister, FpuRegister> { 221 void GenerateClassInitializationCheck(SlowPathCodeMIPS64* slow_path, GpuRegister class_reg); 283 void MarkGCCard(GpuRegister object, GpuRegister value, bool value_can_be_null);
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/art/runtime/arch/mips64/ |
H A D | registers_mips64.cc | 31 std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs) { 35 os << "GpuRegister[" << static_cast<int>(rhs) << "]";
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H A D | registers_mips64.h | 29 enum GpuRegister { enum in namespace:art::mips64 68 std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs);
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/art/compiler/jni/quick/mips64/ |
H A D | calling_convention_mips64.cc | 26 static const GpuRegister kGpuArgumentRegisters[] = { 109 GpuRegister arg = kGpuArgumentRegisters[reg_index];
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