Searched refs:GpuRegister (Results 1 - 10 of 10) sorted by relevance

/art/compiler/utils/mips64/
H A Dassembler_mips64.h122 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
123 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
124 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
125 void Daddiu(GpuRegister rt, GpuRegister r
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H A Dassembler_mips64.cc91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,
105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd,
131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) {
141 void Mips64Assembler::EmitI21(int opcode, GpuRegister r
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H A Dmanaged_register_mips64.h42 GpuRegister AsGpuRegister() const {
44 return static_cast<GpuRegister>(id_);
70 static Mips64ManagedRegister FromGpuRegister(GpuRegister r) {
H A Dassembler_mips64_test.cc32 bool operator()(const mips64::GpuRegister& a, const mips64::GpuRegister& b) const {
38 mips64::GpuRegister,
43 mips64::GpuRegister,
81 registers_.push_back(new mips64::GpuRegister(mips64::ZERO));
82 registers_.push_back(new mips64::GpuRegister(mips64::AT));
83 registers_.push_back(new mips64::GpuRegister(mips64::V0));
84 registers_.push_back(new mips64::GpuRegister(mips64::V1));
85 registers_.push_back(new mips64::GpuRegister(mips64::A0));
86 registers_.push_back(new mips64::GpuRegister(mips6
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/art/compiler/optimizing/
H A Dintrinsics_mips64.cc59 GpuRegister trg_reg = trg.AsRegister<GpuRegister>();
151 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
187 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
226 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
227 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
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H A Dcode_generator_mips64.cc38 static constexpr GpuRegister kMethodRegisterArgument = A0;
476 __ Ld(GpuRegister(reg), SP, 0);
483 __ Sd(GpuRegister(reg), SP, 0);
496 GpuRegister(ensure_scratch.GetRegister()),
504 GpuRegister(ensure_scratch.GetRegister()),
510 static dwarf::Reg DWARFReg(GpuRegister reg) {
553 GpuRegister reg = kCoreCalleeSaves[i];
608 GpuRegister reg = kCoreCalleeSaves[i];
674 destination.AsRegister<GpuRegister>(),
680 GpuRegister gp
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H A Dcode_generator_mips64.h32 static constexpr GpuRegister kParameterCoreRegisters[] =
43 static constexpr GpuRegister kRuntimeParameterCoreRegisters[] =
54 static constexpr GpuRegister kCoreCalleeSaves[] =
62 class InvokeDexCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
90 class InvokeRuntimeCallingConvention : public CallingConvention<GpuRegister, FpuRegister> {
221 void GenerateClassInitializationCheck(SlowPathCodeMIPS64* slow_path, GpuRegister class_reg);
283 void MarkGCCard(GpuRegister object, GpuRegister value, bool value_can_be_null);
/art/runtime/arch/mips64/
H A Dregisters_mips64.cc31 std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs) {
35 os << "GpuRegister[" << static_cast<int>(rhs) << "]";
H A Dregisters_mips64.h29 enum GpuRegister { enum in namespace:art::mips64
68 std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs);
/art/compiler/jni/quick/mips64/
H A Dcalling_convention_mips64.cc26 static const GpuRegister kGpuArgumentRegisters[] = {
109 GpuRegister arg = kGpuArgumentRegisters[reg_index];

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