| /art/test/055-enum-performance/src/ |
| H A D | SamePackagePrivateEnum.java | 2 ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, enum constant in enum:SamePackagePrivateEnum
|
| H A D | SamePackagePublicEnum.java | 2 ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, enum constant in enum:SamePackagePublicEnum
|
| /art/test/055-enum-performance/src/otherpackage/ |
| H A D | OtherPackagePublicEnum.java | 4 ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, enum constant in enum:OtherPackagePublicEnum
|
| /art/runtime/arch/mips/ |
| H A D | registers_mips.cc | 31 if (rhs >= ZERO && rhs <= RA) {
|
| H A D | registers_mips.h | 30 ZERO = 0, enumerator in enum:art::mips::Register
|
| /art/runtime/arch/mips64/ |
| H A D | registers_mips64.cc | 32 if (rhs >= ZERO && rhs < kNumberOfGpuRegisters) {
|
| H A D | registers_mips64.h | 30 ZERO = 0, enumerator in enum:art::mips64::GpuRegister
|
| /art/compiler/utils/mips/ |
| H A D | assembler_mips_test.cc | 57 registers_.push_back(new mips::Register(mips::ZERO));
90 secondary_register_names_.emplace(mips::Register(mips::ZERO), "zero");
196 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
201 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO);
225 __ Addu(mips::ZERO, mips::ZERO, mip
[all...] |
| H A D | assembler_mips.cc | 539 Beq(ZERO, rt, imm16);
543 Bne(ZERO, rt, imm16);
599 Jalr(ZERO, rs);
634 CHECK_NE(rs, ZERO);
635 CHECK_NE(rt, ZERO);
642 CHECK_NE(rt, ZERO);
648 CHECK_NE(rt, ZERO);
654 CHECK_NE(rs, ZERO);
655 CHECK_NE(rt, ZERO);
662 CHECK_NE(rt, ZERO);
[all...] |
| H A D | assembler_mips.h | 656 Register rhs_reg = ZERO);
773 void Bcond(MipsLabel* label, BranchCondition condition, Register lhs, Register rhs = ZERO);
|
| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64_test.cc | 81 registers_.push_back(new mips64::GpuRegister(mips64::ZERO));
114 secondary_register_names_.emplace(mips64::GpuRegister(mips64::ZERO), "zero");
220 __ Addu(mips64::ZERO, mips64::ZERO, mips64::ZERO);
225 __ Addu(mips64::ZERO, mips64::ZERO, mips64::ZERO);
249 __ Addu(mips64::ZERO, mips64::ZERO, mips6
[all...] |
| H A D | assembler_mips64.cc | 111 static_cast<uint32_t>(ZERO) << kRtShift |
123 static_cast<uint32_t>(ZERO) << kRsShift |
530 Jalr(ZERO, rs);
555 CHECK_NE(rs, ZERO);
556 CHECK_NE(rt, ZERO);
562 CHECK_NE(rt, ZERO);
567 CHECK_NE(rt, ZERO);
572 CHECK_NE(rs, ZERO);
573 CHECK_NE(rt, ZERO);
579 CHECK_NE(rt, ZERO);
[all...] |
| H A D | assembler_mips64.h | 570 GpuRegister rhs_reg = ZERO);
689 GpuRegister rhs = ZERO);
|
| /art/compiler/optimizing/ |
| H A D | code_generator_mips.cc | 679 ZERO,
996 // ZERO, K0, K1, GP, SP, RA are always reserved and can't be allocated.
997 blocked_core_registers_[ZERO] = true;
1194 Register rhs_reg = ZERO;
1255 __ Slt(TMP, lhs_low, ZERO);
1431 Register rhs_reg = use_imm ? ZERO : rhs_location.AsRegister<Register>();
1474 __ Subu(TMP, ZERO, rhs_reg);
1546 __ Move(dst_low, ZERO);
1552 __ Move(dst_high, ZERO);
1579 __ Nor(AT, ZERO, rhs_re
[all...] |
| H A D | code_generator_mips64.cc | 525 ZERO,
687 gpr = ZERO;
694 gpr = ZERO;
763 GpuRegister gpr = ZERO;
895 // ZERO, K0, K1, GP, SP, RA are always reserved and can't be allocated.
896 blocked_core_registers_[ZERO] = true;
1070 GpuRegister rhs_reg = ZERO;
1177 GpuRegister rhs_reg = ZERO;
1710 GpuRegister rhs = ZERO;
1860 __ Move(out, ZERO);
[all...] |
| H A D | intrinsics_mips.cc | 458 __ Movn(TMP, ZERO, in_hi);
553 __ Movn(TMP, ZERO, in_lo);
2281 __ Sltu(out, ZERO, out);
2352 __ Movn(out_lo, ZERO, out_hi);
2399 __ Subu(TMP, ZERO, in_lo);
2401 __ Subu(TMP, ZERO, in_hi);
2406 __ Movn(out_hi, ZERO, out_lo);
2412 __ Subu(TMP, ZERO, in);
|
| H A D | intrinsics_mips64.cc | 1675 __ Sltu(out, ZERO, out);
|