| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 518 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
523 FMINNUM, FMAXNUM, enumerator in enum:llvm::ISD::NodeType
524 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that
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| H A D | BasicTTIImpl.h | 648 ISD = ISD::FMAXNUM;
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| H A D | SelectionDAG.h | 1101 case ISD::FMAXNUM:
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| /external/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 789 setOperationAction(ISD::FMAXNUM, VT, Expand);
847 setOperationAction(ISD::FMAXNUM, VT, Expand);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 154 case ISD::FMAXNUM: return "fmaxnum";
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| H A D | LegalizeVectorOps.cpp | 303 case ISD::FMAXNUM:
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| H A D | LegalizeFloatTypes.cpp | 78 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break;
1000 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break;
1873 case ISD::FMAXNUM:
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| H A D | SelectionDAGBuilder.cpp | 2498 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2501 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
2502 Opc = ISD::FMAXNUM;
2506 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
2507 ISD::FMAXNUM : ISD::FMAXNAN;
4790 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5807 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
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| H A D | LegalizeVectorTypes.cpp | 111 case ISD::FMAXNUM:
671 case ISD::FMAXNUM:
2035 case ISD::FMAXNUM:
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| H A D | LegalizeDAG.cpp | 4026 case ISD::FMAXNUM:
4402 case ISD::FMAXNUM:
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| H A D | DAGCombiner.cpp | 1428 case ISD::FMAXNUM: return visitFMAXNUM(N);
4994 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
5005 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
9268 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 84 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
257 setTargetDAGCombine(ISD::FMAXNUM);
1900 case ISD::FMAXNUM:
1994 case ISD::FMAXNUM: // TODO: What about fmax_legacy?
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| H A D | AMDGPUISelLowering.cpp | 93 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
343 setOperationAction(ISD::FMAXNUM, VT, Expand);
965 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 306 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
398 setOperationAction(ISD::FMAXNUM, Ty, Legal);
703 ISD::FMINNUM, ISD::FMAXNUM})
8408 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0),
8801 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) {
8878 case ISD::FMAXNUM:
8947 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM)
8958 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) {
8982 (Op == ISD::FMAXNUM && CC != ISD::SETOGT && CC != ISD::SETOGE &&
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 980 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
982 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
984 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
994 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
2833 ? ISD::FMINNUM : ISD::FMAXNUM;
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1596 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1762 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 706 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
752 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 679 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
1809 setTargetDAGCombine(ISD::FMAXNUM);
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