Searched refs:RefI (Results 1 - 4 of 4) sorted by relevance

/external/llvm/lib/Target/Hexagon/
H A DBitTracker.h110 Ref // Bit value same as the one described in RefI.
132 // as the RefI.Reg is not 0, it may actually be the same register as the
133 // one in which V will be contained. If the RefI.Pos refers to the posi-
137 // If RefI.Reg is 0, however, such a reference to the same register is
138 // not possible. Any value V that is a "ref", and whose RefI.Reg is 0
142 BitRef RefI; member in struct:llvm::BitTracker::BitValue
146 BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {}
151 if (Type == Ref && !(RefI == V.RefI))
180 if (Type == Ref && RefI
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H A DBitTracker.cpp99 OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']';
123 if (IsRef && SV.Type == BT::BitValue::Ref && V.RefI.Reg == SV.RefI.Reg) {
125 SeqRef = (V.RefI.Pos == SV.RefI.Pos+1);
126 ConstRef = (V.RefI.Pos == SV.RefI.Pos);
128 if (SeqRef && V.RefI.Pos == SV.RefI
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H A DHexagonBitSimplify.cpp276 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0)
279 if (RC2[B2+i].Type == BitTracker::BitValue::Ref && RC2[B2+i].RefI.Reg == 0)
1723 unsigned Reg = RC[I].RefI.Reg;
1724 unsigned P = RC[I].RefI.Pos; // The RefI.Pos will be advanced by I-B.
1743 if (RV.RefI.Reg != Reg)
1745 if (RV.RefI.Pos != i+Pos)
2082 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg != RS.Reg) {
2083 const TargetRegisterClass *TC = MRI.getRegClass(V.RefI.Reg);
2084 // Need to map V.RefI
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H A DHexagonGenInsert.cpp238 unsigned Ind1 = BaseOrd[V1.RefI.Reg], Ind2 = BaseOrd[V2.RefI.Reg];
242 assert(V1.RefI.Pos != V2.RefI.Pos && "Bit values should be different");
243 return V1.RefI.Pos < V2.RefI.Pos;
666 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg == VR)
677 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg != VR)

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