/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 402 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, 406 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, 410 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, 414 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, 419 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, 423 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, 427 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, 431 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
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H A D | ARMISelLowering.cpp | 139 setOperationAction(ISD::SDIV, VT, Expand); 559 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 560 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 779 setOperationAction(ISD::SDIV, MVT::i32, LibCall); 6502 "unexpected type for custom-lowering ISD::SDIV"); 6877 case ISD::SDIV: return LowerSDIV(Op, DAG); 6930 case ISD::SDIV: 6932 return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV,
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 98 if (ISD == ISD::SDIV && 121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 224 { ISD::SDIV, MVT::v32i8, 32*20 }, 225 { ISD::SDIV, MVT::v16i16, 16*20 }, 226 { ISD::SDIV, MVT::v8i32, 8*20 }, 227 { ISD::SDIV, MVT::v4i64, 4*20 }, 273 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 282 if (ISD == ISD::SDIV [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 339 case ISD::SDIV: 350 if (N->getOpcode() == ISD::SDIV) { 362 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator in enum:llvm::ISD::NodeType
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H A D | SelectionDAGNodes.h | 1023 case ISD::SDIV:
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 89 case ISD::SDIV: return LowerSDIV(Op, DAG);
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H A D | AMDILISelLowering.cpp | 123 setOperationAction(ISD::SDIV, VT, Custom); 181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 328 if (ISD == ISD::SDIV &&
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/external/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1661 case ISD::SDIV: 1663 DivOpc = Mips::SDIV; 1778 if (!selectBinaryOp(I, ISD::SDIV)) 1779 return selectDivRem(I, ISD::SDIV);
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H A D | MipsSEISelLowering.cpp | 168 setOperationAction(ISD::SDIV, MVT::i32, Legal); 215 setOperationAction(ISD::SDIV, MVT::i64, Legal); 266 setOperationAction(ISD::SDIV, Ty, Legal); 1784 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
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/external/pcre/dist/sljit/ |
H A D | sljitNativeARM_64.c | 109 #define SDIV 0x9ac00c00 macro 1267 FAIL_IF(push_inst(compiler, ((op == SLJIT_UDIVMOD ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN(SLJIT_R0) | RM(SLJIT_R1))); 1272 return push_inst(compiler, ((op == SLJIT_UDIVI ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN(SLJIT_R0) | RM(SLJIT_R1));
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H A D | sljitNativeSPARC_common.c | 171 #define SDIV (OPC1(0x2) | OPC3(0x0f)) macro 794 FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_UDIVI ? UDIV : SDIV) | D(SLJIT_R0) | S1(SLJIT_R0) | S2(SLJIT_R1), DR(SLJIT_R0)));
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/external/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 886 case ISD::SDIV: 1561 case SDiv: return ISD::SDIV;
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 153 setOperationAction(ISD::SDIV, MVT::i8, Expand); 159 setOperationAction(ISD::SDIV, MVT::i16, Expand);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 180 case ISD::SDIV: return "sdiv";
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H A D | FastISel.cpp | 432 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && 1555 return selectBinaryOp(I, ISD::SDIV);
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H A D | LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 264 case ISD::SDIV:
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H A D | LegalizeVectorTypes.cpp | 124 case ISD::SDIV: 674 case ISD::SDIV: 2051 case ISD::SDIV:
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H A D | LegalizeDAG.cpp | 3453 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 3471 case ISD::SDIV: { 3472 bool isSigned = Node->getOpcode() == ISD::SDIV; 4173 case ISD::SDIV:
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H A D | SelectionDAG.cpp | 3213 case ISD::SDIV: 3485 case ISD::SDIV: 3812 case ISD::SDIV: 3840 case ISD::SDIV:
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/external/v8/src/arm64/ |
H A D | disasm-arm64.cc | 600 FORMAT(SDIV, "sdiv");
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H A D | constants-arm64.h | 964 SDIV = SDIV_w, enumerator in enum:v8::internal::DataProcessing2SourceOp
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1690 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, 1748 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
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/external/vixl/src/vixl/a64/ |
H A D | constants-a64.h | 1045 SDIV = SDIV_w, enumerator in enum:vixl::DataProcessing2SourceOp
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