Searched refs:SDIV (Results 1 - 25 of 40) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp402 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
406 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
410 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
414 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
419 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
423 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
427 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
431 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
H A DARMISelLowering.cpp139 setOperationAction(ISD::SDIV, VT, Expand);
559 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
560 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
779 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
6502 "unexpected type for custom-lowering ISD::SDIV");
6877 case ISD::SDIV: return LowerSDIV(Op, DAG);
6930 case ISD::SDIV:
6932 return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV,
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp98 if (ISD == ISD::SDIV &&
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
224 { ISD::SDIV, MVT::v32i8, 32*20 },
225 { ISD::SDIV, MVT::v16i16, 16*20 },
226 { ISD::SDIV, MVT::v8i32, 8*20 },
227 { ISD::SDIV, MVT::v4i64, 4*20 },
273 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
282 if (ISD == ISD::SDIV
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp339 case ISD::SDIV:
350 if (N->getOpcode() == ISD::SDIV) {
362 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator in enum:llvm::ISD::NodeType
H A DSelectionDAGNodes.h1023 case ISD::SDIV:
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp89 case ISD::SDIV: return LowerSDIV(Op, DAG);
H A DAMDILISelLowering.cpp123 setOperationAction(ISD::SDIV, VT, Custom);
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp328 if (ISD == ISD::SDIV &&
/external/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1661 case ISD::SDIV:
1663 DivOpc = Mips::SDIV;
1778 if (!selectBinaryOp(I, ISD::SDIV))
1779 return selectDivRem(I, ISD::SDIV);
H A DMipsSEISelLowering.cpp168 setOperationAction(ISD::SDIV, MVT::i32, Legal);
215 setOperationAction(ISD::SDIV, MVT::i64, Legal);
266 setOperationAction(ISD::SDIV, Ty, Legal);
1784 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
/external/pcre/dist/sljit/
H A DsljitNativeARM_64.c109 #define SDIV 0x9ac00c00 macro
1267 FAIL_IF(push_inst(compiler, ((op == SLJIT_UDIVMOD ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN(SLJIT_R0) | RM(SLJIT_R1)));
1272 return push_inst(compiler, ((op == SLJIT_UDIVI ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN(SLJIT_R0) | RM(SLJIT_R1));
H A DsljitNativeSPARC_common.c171 #define SDIV (OPC1(0x2) | OPC3(0x0f)) macro
794 FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_UDIVI ? UDIV : SDIV) | D(SLJIT_R0) | S1(SLJIT_R0) | S2(SLJIT_R1), DR(SLJIT_R0)));
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp886 case ISD::SDIV:
1561 case SDiv: return ISD::SDIV;
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp153 setOperationAction(ISD::SDIV, MVT::i8, Expand);
159 setOperationAction(ISD::SDIV, MVT::i16, Expand);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp180 case ISD::SDIV: return "sdiv";
H A DFastISel.cpp432 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
1555 return selectBinaryOp(I, ISD::SDIV);
H A DLegalizeVectorOps.cpp15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
264 case ISD::SDIV:
H A DLegalizeVectorTypes.cpp124 case ISD::SDIV:
674 case ISD::SDIV:
2051 case ISD::SDIV:
H A DLegalizeDAG.cpp3453 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3471 case ISD::SDIV: {
3472 bool isSigned = Node->getOpcode() == ISD::SDIV;
4173 case ISD::SDIV:
H A DSelectionDAG.cpp3213 case ISD::SDIV:
3485 case ISD::SDIV:
3812 case ISD::SDIV:
3840 case ISD::SDIV:
/external/v8/src/arm64/
H A Ddisasm-arm64.cc600 FORMAT(SDIV, "sdiv");
H A Dconstants-arm64.h964 SDIV = SDIV_w, enumerator in enum:v8::internal::DataProcessing2SourceOp
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1690 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1748 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
/external/vixl/src/vixl/a64/
H A Dconstants-a64.h1045 SDIV = SDIV_w, enumerator in enum:vixl::DataProcessing2SourceOp

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