| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 377 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
380 SHL_PARTS, SRA_PARTS, SRL_PARTS, enumerator in enum:llvm::ISD::NodeType
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 129 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
130 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 235 case ISD::SHL_PARTS: return "shl_parts";
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| H A D | LegalizeIntegerTypes.cpp | 2249 PartsOpc = ISD::SHL_PARTS;
2257 // Next check to see if the target supports this SHL_PARTS operation or if it
2270 // the new SHL_PARTS operation would need further legalization.
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| H A D | LegalizeDAG.cpp | 1376 case ISD::SHL_PARTS:
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| H A D | SelectionDAG.cpp | 5524 case ISD::SHL_PARTS:
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| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 134 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
|
| /external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 152 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 167 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
170 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
1747 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1755 assert(Op.getOpcode() == ISD::SHL_PARTS);
1829 case ISD::SHL_PARTS:
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 299 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
305 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
884 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 176 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
594 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 105 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1645 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1662 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1692 ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 134 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
2309 case ISD::SHL_PARTS:
4450 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4462 assert(Op.getOpcode() == ISD::SHL_PARTS);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 733 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
4288 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4301 assert(Op.getOpcode() == ISD::SHL_PARTS);
6862 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 398 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
403 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
7989 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 463 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
467 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
12478 if (Op.getOpcode() == ISD::SHL_PARTS) {
12499 if (Op.getOpcode() == ISD::SHL_PARTS) {
20076 case ISD::SHL_PARTS:
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 235 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
|