/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 103 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 106 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 108 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 112 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 116 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 118 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 122 { ISD::SINT_TO_FP, MV [all...] |
H A D | ARMISelLowering.cpp | 104 setOperationAction(ISD::SINT_TO_FP, VT, Custom); 109 setOperationAction(ISD::SINT_TO_FP, VT, Expand); 565 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 569 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 675 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 3946 case ISD::SINT_TO_FP: 3948 Opc = ISD::SINT_TO_FP; 3966 if (Op.getOpcode() == ISD::SINT_TO_FP) 6436 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 6437 Y = DAG.getNode(ISD::SINT_TO_FP, d [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 215 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 216 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 217 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 223 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, 225 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, 231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, 232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 237 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }, 238 { ISD::SINT_TO_FP, MV [all...] |
H A D | AArch64ISelLowering.cpp | 179 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 180 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 181 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); 481 setTargetDAGCombine(ISD::SINT_TO_FP); 558 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); 567 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); 569 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); 572 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote); 574 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote); 577 setOperationAction(ISD::SINT_TO_FP, MV [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 573 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 574 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 575 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 576 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 578 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 579 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 580 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 667 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 668 { ISD::SINT_TO_FP, MV [all...] |
H A D | X86IntrinsicsInfo.h | 507 ISD::SINT_TO_FP, 0), 509 ISD::SINT_TO_FP, 0), // no rm 511 ISD::SINT_TO_FP, 0), 513 ISD::SINT_TO_FP, 0), 515 ISD::SINT_TO_FP, ISD::SINT_TO_FP), //er 577 ISD::SINT_TO_FP, 0), 579 ISD::SINT_TO_FP, 0), 581 ISD::SINT_TO_FP, ISD::SINT_TO_FP), [all...] |
H A D | X86ISelLowering.cpp | 160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 198 setOperationAction(ISD::SINT_TO_FP , MV [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 402 SINT_TO_FP, enumerator in enum:llvm::ISD::NodeType
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 339 case ISD::SINT_TO_FP: 387 case ISD::SINT_TO_FP: 977 // Make sure that the SINT_TO_FP and SRL instructions are available. 978 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || 1005 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); 1007 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
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H A D | LegalizeDAG.cpp | 1244 case ISD::SINT_TO_FP: 2584 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2619 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); 2628 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); 2674 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2728 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2744 // If the target supports SINT_TO_FP of this type, use it. 2745 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2746 OpToUse = ISD::SINT_TO_FP; 3145 case ISD::SINT_TO_FP [all...] |
H A D | LegalizeFloatTypes.cpp | 109 case ISD::SINT_TO_FP: 690 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; 1026 case ISD::SINT_TO_FP: 1393 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; 1396 // First do an SINT_TO_FP, whether the original was signed or unsigned. 1405 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); 1425 // Unsigned - fix up the SINT_TO_FP value just calculated. 1890 case ISD::SINT_TO_FP:
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H A D | LegalizeVectorTypes.cpp | 97 case ISD::SINT_TO_FP: 442 case ISD::SINT_TO_FP: 652 case ISD::SINT_TO_FP: 1434 case ISD::SINT_TO_FP: 2078 case ISD::SINT_TO_FP: 2981 case ISD::SINT_TO_FP:
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H A D | SelectionDAGDumper.cpp | 253 case ISD::SINT_TO_FP: return "sint_to_fp";
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H A D | FastISel.cpp | 244 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, 1626 return selectCast(I, ISD::SINT_TO_FP);
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H A D | LegalizeIntegerTypes.cpp | 896 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 2667 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2940 "Don't know how to expand this SINT_TO_FP!"); 3050 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 3052 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
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H A D | DAGCombiner.cpp | 1417 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 8870 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); 8872 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 8874 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 8927 // but SINT_TO_FP is legal on this target, try to convert. 8929 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 8930 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 8932 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); 8959 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) 8964 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; [all...] |
H A D | SelectionDAG.cpp | 2883 case ISD::SINT_TO_FP: { 2887 Opcode==ISD::SINT_TO_FP, 2997 case ISD::SINT_TO_FP:
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 527 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia); 530 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
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H A D | R600ISelLowering.cpp | 414 ConversionOp = ISD::SINT_TO_FP;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1842 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); 1843 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); 1844 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 1847 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 1848 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); 105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, 111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); 255 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 364 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 371 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 382 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 388 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 511 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 638 setOperationAction(ISD::SINT_TO_FP, MV [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 275 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 309 setOperationAction(ISD::SINT_TO_FP, VT, Expand); 632 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1554 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; 2174 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1524 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1526 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 2936 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, 3346 case ISD::SINT_TO_FP: 3353 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
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/external/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1585 case SIToFP: return ISD::SINT_TO_FP;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 281 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); 1851 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
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