| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_opcode_tmp.h | 157 OP12(UMAX)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUISelLowering.h | 119 UMAX, enumerator in enum:llvm::AMDGPUISD::__anon14091
|
| H A D | AMDGPUISelLowering.cpp | 130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
347 NODE_NAME_CASE(UMAX)
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 262 X86_INTRINSIC_DATA(avx2_pmaxu_b, INTR_TYPE_2OP, ISD::UMAX, 0),
263 X86_INTRINSIC_DATA(avx2_pmaxu_d, INTR_TYPE_2OP, ISD::UMAX, 0),
264 X86_INTRINSIC_DATA(avx2_pmaxu_w, INTR_TYPE_2OP, ISD::UMAX, 0),
966 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
967 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
968 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
969 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
970 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
971 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
972 X86_INTRINSIC_DATA(avx512_mask_pmaxu_q_128, INTR_TYPE_2OP_MASK, ISD::UMAX,
[all...] |
| H A D | X86ISelLowering.cpp | 847 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
1196 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1197 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1198 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1243 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1244 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1245 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1494 setOperationAction(ISD::UMAX, MV
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 322 SMIN, SMAX, UMIN, UMAX, enumerator in enum:llvm::ISD::NodeType
|
| H A D | SelectionDAG.h | 1085 case ISD::UMAX:
|
| /external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/ |
| H A D | sm4_to_tgsi.cpp | 513 OP2(UMAX);
560 OP2_(UMAX, MAX);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 209 case ISD::UMAX: return "umax";
|
| H A D | LegalizeVectorOps.cpp | 333 case ISD::UMAX:
|
| H A D | LegalizeVectorTypes.cpp | 117 case ISD::UMAX:
690 case ISD::UMAX:
2041 case ISD::UMAX:
|
| H A D | SelectionDAG.cpp | 2484 case ISD::UMAX: {
2605 case ISD::UMAX:
3204 case ISD::UMAX: return std::make_pair(C1.uge(C2) ? C1 : C2, true);
3490 case ISD::UMAX:
|
| H A D | LegalizeDAG.cpp | 3351 case ISD::UMAX: {
3358 case ISD::UMAX: Pred = ISD::SETUGT; break;
|
| H A D | LegalizeIntegerTypes.cpp | 81 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
|
| H A D | SelectionDAGBuilder.cpp | 2473 case SPF_UMAX: Opc = ISD::UMAX; break;
|
| H A D | DAGCombiner.cpp | 1381 case ISD::UMAX: return visitIMINMAX(N);
|
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 261 setTargetDAGCombine(ISD::UMAX);
1904 case ISD::UMAX:
1998 case ISD::UMAX:
|
| H A D | AMDGPUISelLowering.cpp | 283 setOperationAction(ISD::UMAX, MVT::i32, Legal);
979 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
|
| /external/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 796 setOperationAction(ISD::UMAX, VT, Expand);
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_from_tgsi.cpp | 536 NV50_IR_OPCODE_CASE(UMAX, MAX);
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 697 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2224 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(),
8869 case ISD::UMAX:
8946 if (Op != ISD::SMAX && Op != ISD::UMAX && Op != ISD::SMIN &&
8979 (Op == ISD::UMAX && CC != ISD::SETUGT && CC != ISD::SETUGE) ||
9862 ReplaceReductionResults(N, Results, DAG, ISD::UMAX, AArch64ISD::UMAXV);
|
| /external/mesa3d/src/mesa/state_tracker/ |
| H A D | st_glsl_to_tgsi.cpp | 661 case3(MAX, IMAX, UMAX);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 148 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2842 ? ISD::UMIN : ISD::UMAX;
|