Searched refs:VT1 (Results 1 - 22 of 22) sorted by relevance

/external/llvm/include/llvm/IR/
H A DLegacyPassNameParser.h90 static int ValLessThan(const PassNameParser::OptionInfo *VT1, argument
92 return std::strcmp(VT1->Name, VT2->Name);
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h110 bool isTruncateFree(EVT VT1, EVT VT2) const override;
121 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DMSP430ISelLowering.cpp1167 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { argument
1168 if (!VT1.isInteger() || !VT2.isInteger())
1171 return (VT1.getSizeInBits() > VT2.getSizeInBits());
1179 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { argument
1181 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
/external/eigen/unsupported/test/
H A DFFTW.cpp28 template <typename VT1,typename VT2>
29 long double fft_rmse( const VT1 & fftbuf,const VT2 & timebuf)
50 template <typename VT1,typename VT2>
51 long double dif_rmse( const VT1 buf1,const VT2 buf2)
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h422 SDVTList getVTList(EVT VT1, EVT VT2);
423 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
424 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
939 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2);
940 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
942 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
944 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
946 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
948 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
950 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
[all...]
/external/kernel-headers/original/uapi/asm-generic/
H A Dtermbits.h106 #define VT1 0040000 macro
/external/kernel-headers/original/uapi/asm-mips/asm/
H A Dtermbits.h126 #define VT1 0040000 macro
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1904 SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) { argument
1905 unsigned Bytes = std::max(VT1.getStoreSize(), VT2.getStoreSize());
1906 Type *Ty1 = VT1.getTypeForEVT(*getContext());
5627 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) { argument
5630 ID.AddInteger(VT1.getRawBits());
5637 Array[0] = VT1;
5645 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) { argument
5648 ID.AddInteger(VT1.getRawBits());
5656 Array[0] = VT1;
5665 SDVTList SelectionDAG::getVTList(EVT VT1, EV argument
5864 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, ArrayRef<SDValue> Ops) argument
5870 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2) argument
5876 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, ArrayRef<SDValue> Ops) argument
5883 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, EVT VT4, ArrayRef<SDValue> Ops) argument
5890 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1) argument
5898 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument
5906 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
5915 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
6086 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2) argument
6092 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1) argument
6100 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) argument
6108 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument
6117 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, ArrayRef<SDValue> Ops) argument
6125 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) argument
6134 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument
6143 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef<SDValue> Ops) argument
6151 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, EVT VT4, ArrayRef<SDValue> Ops) argument
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h115 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DHexagonISelLowering.cpp2068 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { argument
2069 if (!VT1.isSimple() || !VT2.isSimple())
2071 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h286 bool isTruncateFree(EVT VT1, EVT VT2) const override;
291 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DAArch64ISelLowering.cpp6851 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { argument
6852 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6854 unsigned NumBits1 = VT1.getSizeInBits();
6897 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { argument
6898 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6900 unsigned NumBits1 = VT1.getSizeInBits();
6906 EVT VT1 = Val.getValueType(); local
6907 if (isZExtFree(VT1, VT
[all...]
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h125 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h812 bool isTruncateFree(EVT VT1, EVT VT2) const override;
825 bool isZExtFree(EVT VT1, EVT VT2) const override;
838 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
840 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
H A DX86ISelLowering.cpp20750 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20751 if (!VT1.isInteger() || !VT2.isInteger())
20753 unsigned NumBits1 = VT1.getSizeInBits();
20763 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20765 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20769 EVT VT1 = Val.getValueType();
20770 if (isZExtFree(VT1, VT2))
20776 if (!VT1.isSimple() || !VT1.isInteger() ||
20780 switch (VT1
[all...]
/external/llvm/include/llvm/Target/
H A DTargetLowering.h768 EVT VT1;
771 (void)getVectorTypeBreakdown(Context, VT, VT1,
796 EVT VT1;
799 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1694 /// Return true if it's profitable to narrow operations of type VT1 to
1697 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h593 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DPPCISelLowering.cpp11450 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { argument
11451 if (!VT1.isInteger() || !VT2.isInteger())
11453 unsigned NumBits1 = VT1.getSizeInBits();
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp189 EVT VT1 = Val.getValueType();
190 if (!VT1.isSimple() || !VT1.isInteger() ||
194 switch (VT1.getSimpleVT().SimpleTy) {
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp50 for (MVT VT1 : MVT::vector_valuetypes()) {
51 setTruncStoreAction(VT0, VT1, Expand);
52 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
/external/llvm/lib/Transforms/Vectorize/
H A DBBVectorize.cpp1042 Type *VT1 = getVecTypeForPair(IT1, JT1), local
1086 unsigned VCost = getInstrCost(I->getOpcode(), VT1, VT2, Op1VK, Op2VK);
1094 unsigned VParts1 = TTI->getNumberOfParts(VT1),
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp10713 EVT VT1 = Val.getValueType();
10714 if (!VT1.isSimple() || !VT1.isInteger() ||
10718 switch (VT1.getSimpleVT().SimpleTy) {

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