| e7e81714f3ecf67a975d35e74bdb7fd15d924e4d |
|
08-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement the actual tables for texture alignment units [v2]
I implemented functions for horizontal/vertical alignment units separately
because I find it easier to read that way...especially with all the
corner-cases.
[chad] Corrected the vertical alignment calculation by checking for
depthstencil formats.
v2:
- Fix typos in intel_horizontal_texture_alignment_unit():
s/height/width/ and s/VALIGN/HALIGN.
- Remove special case for compressed formats in
intel_get_texture_alignment unit(). Compressed formats are already
handled in the halign and valign functions.
- Replace check ``_mesa_is_depth_format(...) ||
_mesa_is_depthstencil_format(...)`` with explcitit checks against
GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 017c13d55b5b086774d6afea2ca754482c624c6a |
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17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Store miptree alignment units in the miptree
This allows us to replace all the calls to
intel_get_texture_alignment_unit() with a single call at miptree creation.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| d7b33309fe160212f2eb73f471f3aedcb5d0b5c1 |
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15-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Kill intel_mipmap_level::nr_images [v4]
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace "It's" with "Its".
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
v4:
In intel_miptree_get_image_offset(), document the conditions under
which different if-branches are taken.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 669f1822d2a60865514faf37f9fde21e4567b3d2 |
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06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_EXT_texture_array and GL_MESA_texture_array.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 36a91e45f755af164232ef908419bc4cb64ba45b |
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26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence several "warning: unused parameter"
The intel_context and tiling parameters were not used by any if the
i9[14]5_miptree_layout or the functions they call, and the tiling parameter was
not used by brw_miptree_layout. Remove the unnecessary parameters.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| b9fbb9df22ab8ef869730c8b5c1eb79f4f48038e |
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10-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Fix miptree height alignment for compressed NPOT textures.
This is effectively just "round up when dividing by 4" compared to the
previous code. Fixes the broken stripe at the top of
fbo-generatemipmap-formats GL_EXT_texture_compression_rgtc.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 56965aa007c2c6029204d617c0edcf142603e98d |
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10-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop dead preinitialization of align_w, align_h.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 4a60b0c8d2e4890038e1c6a72a7dac3b4cdf996e |
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09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add block alignment for RGTC textures.
We were using the default 4x2 alignment instead of the 4x4 required
for RGTC textures.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 5b3eb7538cd9ceb967b6e9e765896183e7c2c4d4 |
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10-Jan-2011 |
Eric Anholt <eric@anholt.net> |
Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."
This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663.
This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa.
I was wrong about which generations supported baselevel adjustment --
it's just gen4, nothing earlier. This meant that i915 would have
never used the mag filter when baselevel != 0. Not a severe bug, but
not an intentional regression. I think we can fix the performance
issue another way.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 7ce6517f3ac41bf770ab39aba4509d4f535ef663 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Always allocate miptrees from level 0, not tObj->BaseLevel.
BaseLevel/MaxLevel are mostly used for two things: clamping texture
access for FBO rendering, and limiting the used mipmap levels when
incrementally loading textures. By restricting our mipmap trees to
just the current BaseLevel/MaxLevel, we caused reallocation thrashing
in the common case, for a theoretical win if someone really did want
just levels 2..4 or whatever of their texture object.
Bug #30366
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 7d8f0fc28239c8023d2d44cbd4c979aa86c31873 |
|
29-Apr-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix cube map layouts on Ironlake.
We were doubling up the offsets for the mipmap levels for CPU access.
Instead of reimplementing i945_miptree_layout_2d with 6 cube images
separated by qpitch, share that function and provide the level offsets
later.
Fixes piglit cubemap and fbo-cubemap.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 362c1bf75eb74de5b4655c481b74f79718ed4a34 |
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17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Replace mt->pitch with mt->region->pitch.
The pitch is not really an inherent part of the miptree, since it's
not part of any of the layout calculations, and it's dictated by the
libdrm-allocated region pitch now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
|
| 38eddf04ed04966db09b67de4cdabef681dc2696 |
|
06-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove an unneeded hunk that slipped in with texture tiling.
intel_miptree_pitch_align does this later on.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
|
| 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| a183efc132c8db1bb42525ac177ffff96f69a59b |
|
18-Dec-2007 |
Keith Packard <keithp@keithp.com> |
[Intel] Centralize mipmap pitch computations.
mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 4599683b480d295e407725e0fe99c357a0086092 |
|
08-Oct-2007 |
Sergio Monteiro Basto <sergio@sergiomb.no-ip.org> |
i915: Fix undefined ALIGN symbol from 77e0523fb7769df4bf43747e136b1653b2421b97.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 77e0523fb7769df4bf43747e136b1653b2421b97 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
|
| 8ea66fa2ec9eeb6a7e869ff08d713f5e77d795e0 |
|
10-Aug-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965/i915tex: applying right alignment to compressed texture,
which make small textures(4x4,2x2,1x1) work well.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| eb6418b8952f335b6cf58232b5f282fc3e325c7a |
|
19-May-2007 |
Roland Scheidegger <sroland@tungstengraphics.com> |
fix miptree layout (i915) for small compressed mipmaps
This seems to work now. Also fix i945 set_level_info, need to match i915
behaviour for storing mip height, as it's assumed to be the mip width
(in texels) elsewhere and the division by 4 is done later (untested).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| fde908444af5c826bce84203a9cb4273d8341ed0 |
|
14-Dec-2006 |
Michel Dänzer <michel@tungstengraphics.com> |
Fix copy-and-paste-o of my e-mail address.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
|
| 81855f22cd8d8df5bd96fdbd76ff975b6cf4150b |
|
14-Dec-2006 |
Michel Dänzer <michel@tungstengraphics.com> |
Fix some corner cases in i945_miptree_layout_2d().
Based on a patch from Keith Whitwell, with some further fixes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
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| 3416ef303af633668cece0b199b4a8b2388c1e2f |
|
14-Dec-2006 |
Michel Dänzer <michel@tungstengraphics.com> |
Share code to lay out >= 945 style 2D mipmaps between i915tex and i965 drivers.
Use the i965 version as it has some fixes over the i915tex version.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_tex_layout.c
|