/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | FastISel.h | 55 const TargetLowering &TLI; member in class:llvm::FastISel
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H A D | FunctionLoweringInfo.h | 58 const TargetLowering &TLI; member in class:llvm::FunctionLoweringInfo 123 explicit FunctionLoweringInfo(const TargetLowering &TLI);
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H A D | SelectionDAG.h | 137 const TargetLowering &TLI; member in class:llvm::SelectionDAG 204 const TargetLowering &getTargetLoweringInfo() const { return TLI; }
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H A D | SelectionDAGISel.h | 44 const TargetLowering &TLI; member in class:llvm::SelectionDAGISel 59 const TargetLowering &getTargetLowering() { return TLI; }
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/external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/ |
H A D | AddrModeMatcher.h | 12 // specified by TLI for an access to "V" with an access type of AccessTy. This 57 const TargetLowering &TLI; member in class:llvm::AddressingModeMatcher 76 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM) { 87 const TargetLowering &TLI) { 91 AddressingModeMatcher(AddrModeInsts, TLI, AccessTy, 84 Match(Value *V, Type *AccessTy, Instruction *MemoryInst, SmallVectorImpl<Instruction*> &AddrModeInsts, const TargetLowering &TLI) argument
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/external/swiftshader/third_party/LLVM/lib/Analysis/ |
H A D | BasicAliasAnalysis.cpp | 727 const TargetLibraryInfo &TLI = getAnalysis<TargetLibraryInfo>(); local 814 else if (TLI.has(LibFunc::memset_pattern16) &&
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | Analysis.cpp | 75 void llvm::ComputeValueVTs(const TargetLowering &TLI, Type *Ty, argument 81 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy); 86 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets, 93 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy); 95 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets, 103 ValueVTs.push_back(TLI.getValueType(Ty)); 130 const TargetLowering &TLI) { 134 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]); 209 const TargetLowering &TLI) { 272 TLI 129 hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos, const TargetLowering &TLI) argument 208 isInTailCallPosition(ImmutableCallSite CS, Attributes CalleeRetAttr, const TargetLowering &TLI) argument 287 isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, const TargetLowering &TLI) argument [all...] |
H A D | CodePlacementOpt.cpp | 35 const TargetLowering *TLI; member in class:__anon18515::CodePlacementOpt 363 if (!TLI->shouldOptimizeCodePlacement()) 382 unsigned Align = TLI->getPrefLoopAlignment(); 417 TLI = MF.getTarget().getTargetLowering();
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H A D | DwarfEHPrepare.cpp | 39 const TargetLowering *TLI; member in class:__anon18517::DwarfEHPrepare 105 FunctionPass(ID), TM(tm), TLI(TM->getTargetLowering()), 503 const char *RewindName = TLI->getLibcallName(RTLIB::UNWIND_RESUME); 524 CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME)); 684 const char *RewindName = TLI->getLibcallName(RTLIB::UNWIND_RESUME); 710 CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME));
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H A D | ExpandISelPseudos.cpp | 55 const TargetLowering *TLI = MF.getTarget().getTargetLowering(); local 69 TLI->EmitInstrWithCustomInserter(MI, MBB);
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H A D | IfConversion.cpp | 152 const TargetLowering *TLI; member in class:__anon18526::IfConverter 261 TLI = MF.getTarget().getTargetLowering();
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H A D | MachineLICM.cpp | 67 const TargetLowering *TLI; member in class:__anon18536::MachineLICM 317 TLI = TM->getTargetLowering(); 677 RCId = TLI->getRepRegClassFor(VT)->getID(); 678 RCCost = TLI->getRepRegClassCostFor(VT);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinter.cpp | 1084 const TargetLowering *TLI = TM.getTargetLowering(); local 1085 const MCExpr *Base = TLI->getPICJumpTableRelocBaseExpr(MF,JTI,OutContext);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 60 const TargetLowering &TLI; member in class:__anon18564::DAGCombiner 282 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 293 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 300 return TLI.isTypeLegal(VT); 646 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 689 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 718 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 724 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 768 if (TLI 1545 tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations) argument 3868 ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, unsigned ExtOpc, SmallVector<SDNode*, 4> &ExtendNodes, const TargetLowering &TLI) argument [all...] |
H A D | InstrEmitter.h | 34 const TargetLowering *TLI; member in class:llvm::InstrEmitter
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H A D | LegalizeDAG.cpp | 51 const TargetLowering &TLI; member in class:__anon18567::SelectionDAGLegalize 188 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 193 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 336 SelectionDAG &DAG, const TargetLowering &TLI) { 361 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 362 TLI.ShouldShrinkFPConstant(OrigVT)) { 370 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 385 const TargetLowering &TLI) { 395 if (TLI.isTypeLegal(intVT)) { 407 TLI 335 ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, SelectionDAG &DAG, const TargetLowering &TLI) argument 384 ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, const TargetLowering &TLI) argument 496 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, const TargetLowering &TLI) argument [all...] |
H A D | LegalizeTypes.h | 36 const TargetLowering &TLI; member in class:llvm::DAGTypeLegalizer 68 return TLI.getTypeAction(*DAG.getContext(), VT); 73 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal; 120 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 121 ValueTypeActions(TLI.getValueTypeActions()) {
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H A D | LegalizeVectorOps.cpp | 37 const TargetLowering &TLI; member in class:__anon18569::VectorLegalizer 76 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 201 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { 209 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); 249 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); 277 if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) || 278 !TLI.isOperationLegalOrCustom(ISD::XOR, VT) || 279 !TLI.isOperationLegalOrCustom(ISD::OR, VT)) 304 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, VT) || 305 !TLI [all...] |
H A D | LegalizeVectorTypes.cpp | 289 TargetLowering::getExtendForContent(TLI.getBooleanContents(true)); 540 if (TLI.isBigEndian()) 559 if (TLI.isBigEndian()) 564 if (TLI.isBigEndian()) 674 TLI.getTargetData()->getPrefTypeAlignment(VecType); 1040 if (TLI.isBigEndian()) 1326 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1330 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1335 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1374 } while (!TLI 2179 FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align = 0, unsigned WidenEx = 0) argument [all...] |
H A D | ScheduleDAGRRList.cpp | 284 const TargetLowering *TLI, 312 RegClass = TLI->getRepRegClassFor(VT)->getID(); 313 Cost = TLI->getRepRegClassCostFor(VT); 1520 const TargetLowering *TLI; member in class:__anon18577::RegReductionPQBase 1543 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) { 1832 if (!TLI) 1848 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost); 1868 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); 1900 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); 1915 unsigned RCId = TLI 283 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost) argument 3005 const TargetLowering *TLI = &IS->getTargetLowering(); local 3021 const TargetLowering *TLI = &IS->getTargetLowering(); local [all...] |
H A D | ScheduleDAGSDNodes.cpp | 71 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); local 77 SU->SchedulingPref = TLI.getSchedulingPreference(N);
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H A D | SelectionDAG.cpp | 833 return TLI.getTargetData()->getABITypeAlignment(Ty); 838 : TM(tm), TLI(*tm.getTargetLowering()), TSI(*tm.getSelectionDAGInfo()), 945 if (VT.isVector() && TLI.getTypeAction(*getContext(), EltVT) == 947 EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT); 980 return getConstant(Val, TLI.getPointerTy(), isTarget); 1048 EVT PTy = TLI.getPointerTy(); 1124 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1151 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1446 MVT ShTy = TLI.getShiftAmountTy(LHSTy); 1460 std::max((unsigned)TLI 3277 getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG, const TargetLowering &TLI, std::string &Str, unsigned Offset) argument 3345 FindOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit, uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool NonScalarIntSafe, bool MemcpyStrSrc, SelectionDAG &DAG, const TargetLowering &TLI) argument 3429 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 3522 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 3600 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 5862 const TargetLowering &TLI = G->getTargetLoweringInfo(); local [all...] |
H A D | SelectionDAGBuilder.cpp | 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 134 if (TLI.isBigEndian()) 148 if (TLI.isBigEndian()) 154 TLI.getPointerTy())); 165 if (TLI.isBigEndian()) 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 298 TLI.isTypeLegal(ValueVT)) 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 338 assert(TLI 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 596 areValueTypesLegal(const TargetLowering &TLI) argument 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); local 2005 areJTsAllowed(const TargetLowering &TLI) argument 3301 InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, SynchronizationScope Scope, bool Before, DebugLoc dl, SelectionDAG &DAG, const TargetLowering &TLI) argument 3583 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, DebugLoc dl) argument 5618 getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI, const TargetData *TD) const argument 5689 GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI, DebugLoc DL, SDISelAsmOperandInfo &OpInfo, std::set<unsigned> &OutputRegs, std::set<unsigned> &InputRegs) argument [all...] |
H A D | SelectionDAGBuilder.h | 289 // TLI - This is information that describes the available target features we 293 const TargetLowering &TLI; member in class:llvm::SelectionDAGBuilder 336 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
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H A D | SelectionDAGISel.cpp | 143 const TargetLowering &TLI = IS->getTargetLowering(); local 147 if (TLI.getSchedulingPreference() == Sched::Latency) 149 if (TLI.getSchedulingPreference() == Sched::RegPressure) 151 if (TLI.getSchedulingPreference() == Sched::Hybrid) 153 assert(TLI.getSchedulingPreference() == Sched::ILP && 193 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 194 FuncInfo(new FunctionLoweringInfo(TLI)), 702 unsigned Reg = TLI.getExceptionAddressRegister(); 706 Reg = TLI.getExceptionSelectorRegister(); 829 FastIS = TLI 1889 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering &TLI) argument [all...] |