/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | VirtRegMap.h | 138 /// createSpillSlot - Allocate a spill slot for RC from MFI. 139 unsigned createSpillSlot(const TargetRegisterClass *RC); 427 int getEmergencySpillSlot(const TargetRegisterClass *RC); 501 unsigned getFirstUnusedRegister(const TargetRegisterClass *RC) { argument 504 if (allocatableRCRegs[RC][Reg])
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H A D | LocalStackSlotAllocation.cpp | 321 const TargetRegisterClass *RC = TRI->getPointerRegClass(); local 322 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
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H A D | Spiller.cpp | 222 const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg()); local 223 LiveInterval &SI = lss->getOrCreateInterval(SS, RC);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 1785 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) { argument 1786 return MRI.createVirtualRegister(RC); 1807 const TargetRegisterClass *RC) { 1808 unsigned ResultReg = createResultReg(RC); 1816 const TargetRegisterClass *RC, unsigned Op0, 1820 unsigned ResultReg = createResultReg(RC); 1837 const TargetRegisterClass *RC, unsigned Op0, 1842 unsigned ResultReg = createResultReg(RC); 1861 const TargetRegisterClass *RC, unsigned Op0, 1867 unsigned ResultReg = createResultReg(RC); 1806 fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC) argument 1815 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 1836 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 1860 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 1888 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1910 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument 1935 fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm) argument 1954 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1980 fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument 2001 const TargetRegisterClass *RC = MRI.getRegClass(Op0); local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.h | 129 const TargetRegisterClass *RC, 134 int FrameIndex, const TargetRegisterClass *RC,
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/external/mdnsresponder/mDNSWindows/Java/ |
H A D | makefile | 40 RC = rc macro 142 $(RC) /fo $@ $?
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 217 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 220 /// register to be a common subclass of RC and the current register class, 227 const TargetRegisterClass *RC,
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/external/llvm/include/llvm/Analysis/ |
H A D | LazyCallGraph.h | 463 friend raw_ostream &operator<<(raw_ostream &OS, const RefSCC &RC) { argument 466 for (LazyCallGraph::SCC &C : RC) { 471 OS << "..., " << *RC.SCCs.back(); 900 void buildSCCs(RefSCC &RC, node_stack_range Nodes); 906 void connectRefSCC(RefSCC &RC);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonBlockRanges.cpp | 234 auto *RC = *I; local 235 if (RC->isAllocatable()) 237 for (unsigned R : *RC) 271 auto &RC = *MRI.getRegClass(R.Reg); local 272 unsigned PReg = *RC.begin();
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H A D | HexagonEarlyIfConv.cpp | 419 const TargetRegisterClass *RC = MRI->getRegClass(DefR); local 420 if (RC == &Hexagon::PredRegsRegClass) 803 const TargetRegisterClass *RC = MRI->getRegClass(DR); local 804 const MCInstrDesc &D = RC == &IntRegsRegClass ? TII->get(C2_mux) 811 unsigned MuxR = MRI->createVirtualRegister(RC); 964 const TargetRegisterClass *RC = MRI->getRegClass(DefR); local 965 NewR = MRI->createVirtualRegister(RC);
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 189 const CodeGenRegisterClass &RC = *RCs[i]; local 190 if (RC.contains(Reg)) { 191 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes(); 346 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, argument 348 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 283 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument 288 switch (RC->getID()) { 318 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument 325 if (RC == &PPC::F8RCRegClass) 327 else if (RC == &PPC::VRRCRegClass) 329 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector()) 333 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); 886 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; local 887 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 888 SReg = MF.getRegInfo().createVirtualRegister(RC); [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/Target/ |
H A D | TargetLowering.h | 204 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; local 205 assert(RC && "This value type is not natively supported!"); 206 return RC; 216 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; local 217 return RC; 1038 void addRegisterClass(EVT VT, TargetRegisterClass *RC) { 1040 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 1041 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 2016 bool isLegalRC(const TargetRegisterClass *RC) const; 2020 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) cons [all...] |
H A D | TargetInstrInfo.h | 372 const TargetRegisterClass *RC, 384 const TargetRegisterClass *RC, 571 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 369 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 381 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 2570 const TargetRegisterClass *RC; local 2572 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; 2574 RC = Opc != X86::LEA32r ? 2587 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) 2621 NewSrc = MF.getRegInfo().createVirtualRegister(RC); 4292 const TargetRegisterClass *RC = local 4294 if (!RC) 4298 if (X86::GR16RegClass.hasSubClassEq(RC) || 4299 X86::GR32RegClass.hasSubClassEq(RC) || 4300 X86::GR64RegClass.hasSubClassEq(RC)) { 4373 isMaskRegClass(const TargetRegisterClass *RC) argument 4593 getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC, bool load) argument 4607 getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load) argument 4740 getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument 4748 getLoadRegOpcode(unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument 4755 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 4773 storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 4794 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 4809 loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 6382 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); local 6498 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 322 const TargetRegisterClass *RC, int SPAdj) { 324 unsigned Reg = RS->FindUnusedReg(RC); 328 Reg = RS->scavengeRegister(RC, II, SPAdj); 372 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; local 377 Reg = findScratchRegister(II, RS, RC, SPAdj); 465 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; local 466 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 321 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) argument
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/external/llvm/lib/Target/AMDGPU/ |
H A D | R600MachineScheduler.cpp | 214 const TargetRegisterClass *RC) const { 216 return RC->contains(Reg); 218 return MRI->getRegClass(Reg) == RC;
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H A D | SIInstrInfo.cpp | 574 const TargetRegisterClass *RC, 589 if (RI.isSGPRClass(RC)) { 592 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && RC->getSize() == 4) { 601 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize()); 620 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); 622 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize()); 672 const TargetRegisterClass *RC, 687 if (RI.isSGPRClass(RC)) { 690 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize()); 692 if (TargetRegisterInfo::isVirtualRegister(DestReg) && RC 570 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 669 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 216 unsigned RC; local 217 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC); 218 if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
H A D | BlackfinRegisterInfo.cpp | 180 const TargetRegisterClass *RC, 183 unsigned Reg = RS->FindUnusedReg(RC); 185 Reg = RS->scavengeRegister(RC, II, SPAdj); 178 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 301 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 303 DenseMap<unsigned, unsigned> &RegMap = VRegMapping[RC]; 309 if (RC == &NVPTX::Int1RegsRegClass) { 311 } else if (RC == &NVPTX::Int16RegsRegClass) { 313 } else if (RC == &NVPTX::Int32RegsRegClass) { 315 } else if (RC == &NVPTX::Int64RegsRegClass) { 317 } else if (RC == &NVPTX::Float32RegsRegClass) { 319 } else if (RC == &NVPTX::Float64RegsRegClass) { 564 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local 569 VRegRCMap::const_iterator I = VRegMapping.find(RC); 1672 const TargetRegisterClass *RC = MRI->getRegClass(vr); local 1691 const TargetRegisterClass *RC = TRI->getRegClass(i); local [all...] |
/external/clang/include/clang/AST/ |
H A D | RawCommentList.h | 186 void addComment(const RawComment &RC, llvm::BumpPtrAllocator &Allocator);
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/external/llvm/include/llvm/CodeGen/ |
H A D | FunctionLoweringInfo.h | 291 const TargetRegisterClass *RC);
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H A D | Passes.h | 308 /// The pass will examine instructions using and defining registers in RC. 310 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 250 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 788 const TargetRegisterClass *RC, 800 const TargetRegisterClass *RC, 1117 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 785 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 797 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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