Searched refs:IndexReg (Results 1 - 24 of 24) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h45 unsigned IndexReg; member in struct:llvm::SystemZAddressMode
49 SystemZAddressMode() : BaseType(RegBase), IndexReg(0), Disp(0) {
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
H A DSystemZISelDAGToDAG.cpp47 SDValue IndexReg; member in struct:__anon18824::SystemZRRIAddressMode
52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
68 errs() << "IndexReg ";
69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
232 if (AM.IndexReg.getNode() || AM.isRI) {
249 AM.IndexReg = Neg;
281 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
283 AM.IndexReg = N.getNode()->getOperand(1);
322 if (AM.IndexReg
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/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp111 const MCOperand &IndexReg = MI->getOperand(Op+2); local
123 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
130 if (IndexReg.getReg() || BaseReg.getReg()) {
135 if (IndexReg.getReg()) {
H A DX86IntelInstPrinter.cpp99 const MCOperand &IndexReg = MI->getOperand(Op+2); local
117 if (IndexReg.getReg()) {
132 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86InstrBuilder.h50 unsigned IndexReg; member in struct:llvm::X86AddressMode
56 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
H A DX86ISelDAGToDAG.cpp64 SDValue IndexReg; member in struct:__anon18871::X86ISelAddressMode
76 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
113 << "IndexReg ";
114 if (IndexReg.getNode() != 0)
115 IndexReg.getNode()->dump();
237 Index = AM.IndexReg;
708 AM.Base_Reg = AM.IndexReg;
720 AM.IndexReg.getNode() == 0 &&
785 if (AM.IndexReg
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H A DX86CodeEmitter.cpp469 const MachineOperand &IndexReg = MI.getOperand(Op+2);
476 assert(IndexReg.getReg() == 0 && Is64BitMode &&
497 IndexReg.getReg() == 0 &&
535 assert(IndexReg.getReg() != X86::ESP &&
536 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
569 if (IndexReg.getReg())
570 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
577 if (IndexReg.getReg())
578 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
H A DX86FastISel.cpp397 unsigned IndexReg = AM.IndexReg; local
434 if (IndexReg == 0 &&
439 IndexReg = getRegForGEPIndex(Op).first;
440 if (IndexReg == 0)
453 AM.IndexReg = IndexReg;
492 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
511 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
573 if (AM.IndexReg
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H A DX86AsmPrinter.cpp283 const MachineOperand &IndexReg = MI->getOperand(Op+2); local
293 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
309 assert(IndexReg.getReg() != X86::ESP &&
316 if (IndexReg.getReg()) {
H A DX86ISelLowering.cpp11671 .addReg(/*IndexReg=*/0)
12086 AM.IndexReg = Op.getImm();
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h49 unsigned IndexReg; member in struct:llvm::X86AddressMode
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
104 AM.IndexReg = Op.getImm();
162 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
H A DX86AsmPrinter.cpp232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
242 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
262 assert(IndexReg.getReg() != X86::ESP &&
269 if (IndexReg.getReg()) {
298 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
316 if (IndexReg.getReg()) {
329 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
H A DX86ISelDAGToDAG.cpp62 SDValue IndexReg; member in struct:__anon13235::X86ISelAddressMode
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
113 << "IndexReg ";
114 if (IndexReg.getNode())
115 IndexReg.getNode()->dump();
254 Index = AM.IndexReg;
847 AM.Base_Reg = AM.IndexReg;
859 AM.IndexReg.getNode() == nullptr &&
890 !AM.IndexReg
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H A DX86FastISel.cpp253 /// IndexReg field of the addressing mode will be updated to match in this case.
258 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg,
722 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
741 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
803 if (AM.IndexReg == 0) {
805 AM.IndexReg = getRegForValue(V);
806 return AM.IndexReg != 0;
890 unsigned IndexReg = AM.IndexReg; local
3768 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), local
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H A DX86MCInstLower.cpp780 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; local
781 Opc = IndexReg = Displacement = SegmentReg = 0;
791 IndexReg = X86::RAX; break;
793 IndexReg = X86::RAX; break;
796 IndexReg = X86::RAX; break;
798 IndexReg = X86::RAX; break;
800 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
823 .addReg(IndexReg)
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp198 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); local
212 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
219 if (IndexReg.getReg() || BaseReg.getReg()) {
224 if (IndexReg.getReg()) {
H A DX86IntelInstPrinter.cpp161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
179 if (IndexReg.getReg()) {
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/external/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h56 unsigned IndexReg; member in struct:llvm::X86Operand::MemOp
121 return Mem.IndexReg;
238 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
504 Res->Mem.IndexReg = 0;
517 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
522 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
531 Res->Mem.IndexReg = IndexReg;
516 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(), void *OpDecl = nullptr) argument
H A DX86AsmParser.cpp264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon13205::X86AsmParser::IntelExprStateMachine
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
279 unsigned getIndexReg() { return IndexReg; }
382 // If we already have a BaseReg, then assume this is the IndexReg with
387 assert (!IndexReg && "BaseReg/IndexReg already set!");
388 IndexReg = TmpReg;
419 // If we already have a BaseReg, then assume this is the IndexReg with
424 assert (!IndexReg && "BaseReg/IndexReg alread
831 CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, StringRef &ErrMsg) argument
1159 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1440 int IndexReg = SM.getIndexReg(); local
2054 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
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/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp136 unsigned IndexReg; member in struct:__anon18835::X86Operand::__anon18836::__anon18840
185 return Mem.IndexReg;
345 Res->Mem.IndexReg = 0;
352 unsigned BaseReg, unsigned IndexReg,
356 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
365 Res->Mem.IndexReg = IndexReg;
380 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
389 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
581 unsigned BaseReg = 0, IndexReg local
351 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) argument
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp163 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
167 (IndexReg.getReg() != 0 &&
168 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
249 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
255 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
286 IndexReg.getReg() == 0 &&
325 assert(IndexReg.getReg() != X86::ESP &&
326 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
362 if (IndexReg.getReg())
363 IndexRegNo = GetX86RegNum(IndexReg);
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/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); local
69 (IndexReg.getReg() != 0 &&
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
207 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
211 (IndexReg.getReg() != 0 &&
212 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
215 assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
226 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
230 (IndexReg.getReg() != 0 &&
231 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg
357 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); local
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp163 unsigned &IndexReg);
433 unsigned &IndexReg) {
454 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
455 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
519 unsigned IndexReg = 0; local
520 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
583 .addReg(Addr.Base.Reg).addReg(IndexReg);
655 unsigned IndexReg = 0; local
656 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
722 if (IndexReg)
432 PPCSimplifyAddress(Address &Addr, bool &UseOffset, unsigned &IndexReg) argument
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5255 unsigned IndexReg = MI.getOperand(3).getReg();
5265 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
5297 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);

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