/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86GenDAGISel.inc | 60 /*94*/ OPC_CheckChild1Type, MVT::v2f64,
70 // Src: (st VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
71 // Dst: (VMOVNTPDmr addr:iPTR:$dst, VR128:v2f64:$src)
75 // Src: (st VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
76 // Dst: (VMOVNTDQ_64mr addr:iPTR:$dst, VR128:v2f64:$src)
85 // Src: (st VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
86 // Dst: (MOVNTPDmr addr:iPTR:$dst, VR128:v2f64:$src)
90 // Src: (st VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
91 // Dst: (MOVNTDQ_64mr addr:iPTR:$dst, VR128:v2f64:$src)
3829 /*SwitchType*/ 56, MVT::v2f64,// [all...] |
H A D | X86GenFastISel.inc | 657 if (RetVT.SimpleTy != MVT::v2f64)
684 case MVT::v2f64: return FastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
1380 if (RetVT.SimpleTy != MVT::v2f64)
1394 case MVT::v2f64: return FastEmit_X86ISD_VZEXT_MOVL_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
1651 if (RetVT.SimpleTy != MVT::v2f64)
1678 case MVT::v2f64: return FastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1744 if (RetVT.SimpleTy != MVT::v2f64)
1771 case MVT::v2f64: return FastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1837 if (RetVT.SimpleTy != MVT::v2f64)
1864 case MVT::v2f64 [all...] |
H A D | X86ISelLowering.cpp | 807 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 826 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 844 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 867 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 869 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custo [all...] |
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/useful-harnesses/ |
H A D | vecoperations.c | 8 typedef double v2f64 __attribute__((ext_vector_type(2))); typedef 62 void print_v2f64(const char *str, v2f64 v) { 131 v2f64 v2f64_shuffle(v2f64 a) { 132 v2f64 c2 = a.yx; 148 v2f64 v4 = { 5.8e56, 9.103e-62 };
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMCallingConv.h | 38 // For the 2nd half of a v2f64, do not fail. 65 if (LocVT == MVT::v2f64 && 81 // For the 2nd half of a v2f64, do not just fail. 113 if (LocVT == MVT::v2f64 && 145 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
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H A D | ARMISelLowering.cpp | 166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 452 addQRTypeForNEON(MVT::v2f64); 458 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 460 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 462 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 463 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 464 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 465 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 466 setOperationAction(ISD::SETCC, MVT::v2f64, Expan [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 217 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 220 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 246 // Complex: to v2f64 247 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 248 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, 249 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 250 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 251 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, 252 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 258 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 2765 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2792 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2819 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2846 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2873 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2900 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2927 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2954 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2981 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { 2998 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 74 v2f64 = 31, // 2 x f64 enumerator in enum:llvm::MVT::SimpleValueType 209 case v2f64: 237 case v2f64: return 2; 277 case v2f64: return 128; 368 if (NumElements == 2) return MVT::v2f64; 497 V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 83 { ISD::FP_ROUND, MVT::v2f64, 2 }, 161 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 162 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 164 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 165 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 166 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 167 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 168 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 169 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 171 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, [all...] |
H A D | ARMCallingConv.h | 37 // For the 2nd half of a v2f64, do not fail. 64 if (LocVT == MVT::v2f64 && 86 // For the 2nd half of a v2f64, do not just fail. 118 if (LocVT == MVT::v2f64 && 150 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) 226 case MVT::v2f64:
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H A D | ARMISelLowering.cpp | 159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 472 addQRTypeForNEON(MVT::v2f64); 478 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 482 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 483 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 484 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 487 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 488 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 492 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 495 setOperationAction(ISD::SETCC, MVT::v2f64, Expan [all...] |
/external/clang/test/CodeGen/ |
H A D | systemz-abi-vector.c | 33 typedef __attribute__((vector_size(16))) double v2f64; typedef 122 v2f64 pass_v2f64(v2f64 arg) { return arg; }
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H A D | builtins-mips-msa.c | 15 typedef double v2f64 __attribute__ ((vector_size(16))); typedef 50 v2f64 v2f64_a = (v2f64) {0.5, 1}; 51 v2f64 v2f64_b = (v2f64) {1.5, 2}; 52 v2f64 v2f64_r;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 65 (int)MVT::v2f64, 93 (int)MVT::v2f64, 188 // we support loading/storing v2f64 but not operations on the type 189 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 190 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 191 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 192 setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand); 193 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); 197 setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand); 198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expan [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineValueType.h | 116 v2f64 = 61, // 2 x f64 252 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); 365 case v2f64: 418 case v2f64: return 2; 489 case v2f64: return 128; 657 if (NumElements == 2) return MVT::v2f64;
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 465 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 487 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd 505 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd 536 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 545 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 588 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 593 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 599 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 606 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 695 { ISD::UINT_TO_FP, MVT::v2f64, MV [all...] |
/external/swiftshader/third_party/LLVM/lib/VMCore/ |
H A D | ValueTypes.cpp | 139 case MVT::v2f64: return "v2f64"; 186 case MVT::v2f64: return VectorType::get(Type::getDoubleTy(Context), 2);
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/external/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 193 case MVT::v2f64: return "v2f64"; 271 case MVT::v2f64: return VectorType::get(Type::getDoubleTy(Context), 2);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 560 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); 561 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); 576 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); 578 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); 579 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); 580 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); 581 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); 582 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); 586 setOperationAction(ISD::MUL, MVT::v2f64, Legal); 587 setOperationAction(ISD::FMA, MVT::v2f64, Lega [all...] |
H A D | PPCTargetTransformInfo.cpp | 371 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelDAGToDAG.cpp | 603 case MVT::v2f64: 796 && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) { 805 if (OpVT == MVT::v2f64) 821 } else if (OpVT == MVT::v2f64) { 835 } else if (OpVT == MVT::v2f64) {
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/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 481 DecodeInsertElementMask(MVT::v2f64, 1, 1, ShuffleMask); 497 DecodeInsertElementMask(MVT::v2f64, 0, 1, ShuffleMask); 881 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask); 949 DecodeSubVectorBroadcast(MVT::v4f64, MVT::v2f64, ShuffleMask);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 110 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass); 343 // There should be no need to check for float types other than v2f64 382 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); 387 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 392 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 393 setOperationAction(ISD::FNEG, MVT::v2f64, Legal); 394 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 395 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 396 setOperationAction(ISD::FMA, MVT::v2f64, Lega [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 216 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) 289 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
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