/system/core/libpixelflinger/codeflinger/ |
H A D | Arm64Assembler.cpp | 365 int imm = mAddrMode.immediate; local 366 *mPC++ = A64_MOVZ_W(mTmpReg2, imm & 0x0000FFFF, 0); 367 *mPC++ = A64_MOVK_W(mTmpReg2, (imm >> 16) & 0x0000FFFF, 16); 483 int imm = mAddrMode.immediate; local 484 *mPC++ = A64_MOVZ_W(mTmpReg1, imm & 0x0000FFFF, 0); 485 *mPC++ = A64_MOVK_W(mTmpReg1, (imm >> 16) & 0x0000FFFF, 16); 586 int imm = mAddrMode.immediate; local 587 if(imm >= 0 && imm < (1<<12)) 588 *mPC++ = A64_ADD_IMM_X(mTmpReg1, mZeroReg, imm, 842 uint32_t imm = 0x00FF00FF; local 859 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument 870 uint32_t rot, imm; local 874 uint32_t ArmToArm64Assembler::imm(uint32_t immediate) function in class:android::ArmToArm64Assembler 1081 A64_ADD_IMM_X(uint32_t Rd, uint32_t Rn, uint32_t imm, uint32_t shift) argument 1088 A64_SUB_IMM_X(uint32_t Rd, uint32_t Rn, uint32_t imm, uint32_t shift) argument 1176 A64_MOVZ_X(uint32_t Rd, uint32_t imm, uint32_t shift) argument 1183 A64_MOVK_W(uint32_t Rd, uint32_t imm, uint32_t shift) argument 1190 A64_MOVZ_W(uint32_t Rd, uint32_t imm, uint32_t shift) argument [all...] |
H A D | ARMAssembler.cpp | 444 uint32_t immediate, uint32_t& rot, uint32_t& imm) 447 imm = immediate; 448 if (imm > 0x7F) { // skip the easy cases 449 while (!(imm&3) || (imm&0xFC000000)) { 451 newval = imm >> 2; 452 newval |= (imm&3) << 30; 453 imm = newval; 463 if (imm>=0x100) 466 if (((imm>>(ro 443 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument 476 uint32_t rot, imm; local 480 uint32_t ARMAssembler::imm(uint32_t immediate) function in class:android::ARMAssembler 482 uint32_t rot, imm; local [all...] |
H A D | texturing.cpp | 161 parts.iterated.reg, imm(0xFF)); 521 SUB(AL, 0, u, u, imm(1<<(FRAC_BITS-1))); 522 SUB(AL, 0, v, v, imm(1<<(FRAC_BITS-1))); 525 AND(AL, 0, U, u, imm((1<<FRAC_BITS)-1)); 526 AND(AL, 0, V, v, imm((1<<FRAC_BITS)-1)); 529 SUB(AL, 0, width, width, imm(1)); 530 SUB(AL, 0, height, height, imm(1)); 539 MOV(LT, 0, width, imm(1 << shift)); 542 RSB(GE, 0, width, width, imm(0)); 559 MOV(LE, 0, width, imm( [all...] |
H A D | mips64_disassem.c | 376 print_addr(loc + 4 + ((short)i.IType.imm << 2)); 485 db_printf("%d(%s)", (short)i.IType.imm, 494 i.IType.imm); 502 i.IType.imm); 508 i.IType.imm); 512 (short)i.IType.imm); 521 (short)i.IType.imm); 529 (short)i.IType.imm);
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H A D | mips_disassem.c | 376 print_addr(loc + 4 + ((short)i.IType.imm << 2)); 485 db_printf("%d(%s)", (short)i.IType.imm, 494 i.IType.imm); 502 i.IType.imm); 508 i.IType.imm); 515 i.IType.imm, 526 (short)i.IType.imm); 534 (short)i.IType.imm);
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H A D | Arm64Assembler.h | 80 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm); 82 virtual uint32_t imm(uint32_t immediate); 210 uint32_t imm, uint32_t shift = 0); 212 uint32_t imm, uint32_t shift = 0); 228 uint32_t A64_MOVZ_W(uint32_t Rd, uint32_t imm, uint32_t shift); 229 uint32_t A64_MOVZ_X(uint32_t Rd, uint32_t imm, uint32_t shift); 230 uint32_t A64_MOVK_W(uint32_t Rd, uint32_t imm, uint32_t shift);
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H A D | MIPSAssembler.h | 65 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm); 67 virtual uint32_t imm(uint32_t immediate); 274 void ADDIU(int Rt, int Rs, int16_t imm); 276 void SUBIU(int Rt, int Rs, int16_t imm); 295 void SLTI(int Rt, int Rs, int16_t imm); 297 void SLTIU(int Rt, int Rs, int16_t imm); 306 void ANDI(int Rd, int Rs, uint16_t imm); 308 void ORI(int Rt, int Rs, uint16_t imm); 312 void XORI(int Rt, int Rs, uint16_t imm);
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H A D | blending.cpp | 57 CMP(AL, factor.reg, imm( 0x10000 )); 58 MOV(HS, 0, factor.reg, imm( 0x10000 )); 299 RSB(AL, 0, factor.reg, factor.reg, imm((1<<factor.s))); 366 RSB(AL, 0, factor.reg, factor.reg, imm((1<<factor.s))); 659 CMP(AL, v.reg, imm( 1<<v.h )); 661 MOV(HS, 0, v.reg, imm( one )); 663 MVN(HS, 0, v.reg, imm( ~one )); 665 MOV(HS, 0, v.reg, imm( 1<<v.h )); 666 SUB(HS, 0, v.reg, v.reg, imm( 1<<v.l ));
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H A D | mips_opcode.h | 52 unsigned imm: 16; member in struct:__anon1578::__anon1579 87 unsigned imm: 16; member in struct:__anon1578::__anon1583
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H A D | GGLAssembler.cpp | 212 imm( 1 << (32 - GGL_DITHER_ORDER_SHIFT))); 266 AND(AL, 0, parts.dither.reg, parts.count.reg, imm(mask)); 325 SUB(AL, S, parts.count.reg, parts.count.reg, imm(1<<16)); 340 ADDR_ADD(AL, 0, parts.cbPtr.reg, parts.cbPtr.reg, imm(parts.cbPtr.size>>3)); 342 SUB(AL, S, parts.count.reg, parts.count.reg, imm(1<<16)); 369 SUB(AL, 0, parts.count.reg, parts.count.reg, imm(1)); 379 AND(AL, 0, tx, Rx, imm(GGL_DITHER_MASK)); 380 AND(AL, 0, ty, Ry, imm(GGL_DITHER_MASK)); 833 case GGL_CLEAR: MOV(AL, 0, pixel.reg, imm(0)); break; 855 case GGL_SET: MVN(AL, 0, pixel.reg, imm( [all...] |
H A D | MIPSAssembler.cpp | 43 ** Refactored ARM address-mode static functions (imm(), reg_imm(), imm12_pre(), etc.) 206 uint32_t immediate, uint32_t& rot, uint32_t& imm) 210 imm = immediate; 222 uint32_t ArmToMipsAssembler::imm(uint32_t immediate) function in class:android::ArmToMipsAssembler 368 // this works with the imm(), reg_imm() methods above, which are directly 1439 // MD00086 pdf says this is: ADDIU rt, rs, imm -- they do not use Rd 1440 void MIPSAssembler::ADDIU(int Rt, int Rs, int16_t imm) argument 1442 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16); 1453 void MIPSAssembler::SUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j) argument 1455 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm) 205 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument 1527 SLTI(int Rt, int Rs, int16_t imm) argument 1539 SLTIU(int Rt, int Rs, int16_t imm) argument 1557 ANDI(int Rt, int Rs, uint16_t imm) argument 1569 ORI(int Rt, int Rs, uint16_t imm) argument 1591 XORI(int Rt, int Rs, uint16_t imm) argument [all...] |
H A D | ARMAssemblerProxy.cpp | 81 int ARMAssemblerProxy::buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm) argument 83 return mTarget->buildImmediate(i, rot, imm); 88 uint32_t ARMAssemblerProxy::imm(uint32_t immediate) function in class:android::ARMAssemblerProxy 90 return mTarget->imm(immediate);
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H A D | MIPS64Assembler.h | 70 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm); 72 virtual uint32_t imm(uint32_t immediate); 274 void DADDIU(int Rt, int Rs, int16_t imm); 276 void DSUBIU(int Rt, int Rs, int16_t imm);
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H A D | load_store.cpp | 52 ADD(AL, 0, addr.reg, addr.reg, imm(3)); 96 ADD(AL, 0, addr.reg, addr.reg, imm(3)); 123 AND(AL, 0, d.reg, s, imm(mask)); // component = packed & mask; 125 BIC(AL, 0, d.reg, s, imm(~mask)); // component = packed & mask;
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H A D | ARMAssembler.h | 67 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm); 69 virtual uint32_t imm(uint32_t immediate);
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H A D | ARMAssemblerProxy.h | 56 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm); 58 virtual uint32_t imm(uint32_t immediate);
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H A D | MIPS64Assembler.cpp | 198 uint32_t immediate, uint32_t& rot, uint32_t& imm) 202 imm = immediate; 214 uint32_t ArmToMips64Assembler::imm(uint32_t immediate) function in class:android::ArmToMips64Assembler 355 // this works with the imm(), reg_imm() methods above, which are directly 1382 void MIPS64Assembler::DADDIU(int Rt, int Rs, int16_t imm) argument 1384 *mPC++ = (daddiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16); 1393 void MIPS64Assembler::DSUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j) argument 1395 *mPC++ = (daddiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm) & MSK_16); 197 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument
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H A D | ARMAssemblerInterface.h | 78 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm) = 0; 80 virtual uint32_t imm(uint32_t immediate) = 0;
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/system/core/libpixelflinger/tests/arch-arm64/assembler/ |
H A D | arm64_assembler_test.cpp | 435 op2 = a64asm->imm(test.immValue); 683 uint32_t op2 = a64asm->imm(0x31);
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/system/core/libpixelflinger/tests/arch-mips64/assembler/ |
H A D | mips64_assembler_test.cpp | 397 op2 = a64asm->imm(test.immValue);
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