/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument 87 unsigned Group2 = GetGroup(Reg2);
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H A D | TargetInstrInfoImpl.cpp | 79 unsigned Reg2 = MI->getOperand(Idx2).getReg(); local 87 Reg0 = Reg2; 88 } else if (HasDef && Reg0 == Reg2 && 101 .addReg(Reg2, getKillRegState(Reg2IsKill)) 105 .addReg(Reg2, getKillRegState(Reg2IsKill)) 112 MI->getOperand(Idx1).setReg(Reg2);
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H A D | StrongPHIElimination.cpp | 441 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { argument 443 Node *Node2 = RegNodeMap[Reg2]->getLeader();
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZInstrBuilder.h | 84 unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) { 86 .addReg(Reg2, getKillRegState(isKill2)); 83 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
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/external/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument 86 unsigned Group2 = GetGroup(Reg2);
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H A D | TargetInstrInfo.cpp | 145 unsigned Reg2 = MI.getOperand(Idx2).getReg(); local 160 Reg0 = Reg2; 162 } else if (HasDef && Reg0 == Reg2 && 183 CommutedMI->getOperand(Idx1).setReg(Reg2);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXFMAMutate.cpp | 189 unsigned Reg2 = MI->getOperand(2).getReg(); local 191 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() 192 && Reg2 != OldFMAReg) {
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H A D | PPCVSXSwapRemoval.cpp | 867 unsigned Reg2 = MI->getOperand(2).getReg(); local 868 MI->getOperand(1).setReg(Reg2);
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H A D | PPCInstrInfo.cpp | 350 unsigned Reg2 = MI.getOperand(2).getReg(); local 378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); 382 .addReg(Reg2, getKillRegState(Reg2IsKill)) 389 MI.getOperand(0).setReg(Reg2); 393 MI.getOperand(1).setReg(Reg2);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 145 unsigned Reg2, bool isKill2) { 147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); 143 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 119 unsigned Reg2 = MI->getOperand(2).getReg(); local 139 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 143 .addReg(Reg2, getKillRegState(Reg2IsKill)) 150 MI->getOperand(0).setReg(Reg2); 152 MI->getOperand(1).setReg(Reg2);
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) { 119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); 115 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
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H A D | X86FastISel.cpp | 1453 unsigned Reg2 = getRegForValue(Op2); local 1455 if (Reg1 == 0 || Reg2 == 0) 1471 .addReg(Reg1).addReg(Reg2);
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AsmBackend.cpp | 454 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); variable 465 Reg2 = getXRegFromWReg(Reg2); 467 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && 470 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && 473 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && 476 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && 479 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && 484 Reg2 = getDRegFromBReg(Reg2); [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 86 unsigned Reg2); 461 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { 469 .addReg(Reg2) 459 createRegSequence( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg1, unsigned Reg2) argument
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H A D | Thumb2SizeReduction.cpp | 710 unsigned Reg2 = MI->getOperand(2).getReg(); local 713 || !isARMLowRegister(Reg2)) 715 if (Reg0 != Reg2) { 745 unsigned Reg2 = MI->getOperand(2).getReg(); local 746 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
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H A D | ARMFastISel.cpp | 2776 unsigned Reg2 = 0; local 2778 Reg2 = getRegForValue(Src2Value); 2779 if (Reg2 == 0) return false; 2792 MIB.addReg(Reg2);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 874 RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {} 876 unsigned Reg2; member in struct:RegPairInfo 880 bool isPaired() const { return Reg2 != AArch64::NoRegister; } 916 RPI.Reg2 = NextReg; 934 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || 935 RPI.Reg1 + 1 == RPI.Reg2))) && 975 unsigned Reg2 = RPI.Reg2; local 994 dbgs() << ", " << TRI->getName(Reg2); 1003 MBB.addLiveIn(Reg2); 1038 unsigned Reg2 = RPI.Reg2; local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 607 unsigned Reg2 = MI->getOperand(2).getReg(); local 608 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 181 unsigned Reg2, SMLoc IDLoc, 183 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); 180 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsAsmPrinter.cpp | 770 unsigned Reg2) { 779 Reg1 = Reg2; 780 Reg2 = Temp; 784 I.addOperand(MCOperand::createReg(Reg2)); 790 unsigned Reg2, unsigned Reg3) { 794 I.addOperand(MCOperand::createReg(Reg2)); 801 unsigned Reg2, unsigned FPReg1, 805 Reg1 = Reg2; 806 Reg2 = temp; 809 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg 768 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) argument 788 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) argument 799 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) argument [all...] |
/external/swiftshader/third_party/LLVM/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 620 CodeGenRegister *Reg2 = i1->second; local 622 if (Reg1 == Reg2) 624 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); 631 if (Reg2 == Reg3) 714 CodeGenRegister *Reg2 = getReg(RegList[i2]); local 715 CodeGenRegister::Set &Overlaps2 = Map[Reg2]; 716 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs(); 717 // Reg overlaps Reg2 which implies it overlaps supers(Reg2). 718 Overlaps.insert(Reg2); [all...] |
/external/llvm/lib/MC/ |
H A D | MCDwarf.cpp | 1042 unsigned Reg2 = Instr.getRegister2(); local 1045 Reg2 = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg2, true), false); 1049 Streamer.EmitULEB128IntValue(Reg2);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1131 CodeGenRegister *Reg2 = i1->second; local 1133 if (&Reg1 == Reg2) 1135 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); 1142 if (Reg2 == Reg3)
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1795 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); local 1796 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2317 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), local 2319 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
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