/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyReplacePhysRegs.cpp | 83 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); local 89 VReg = MRI.createVirtualRegister(RC);
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H A D | WebAssemblyInstrInfo.cpp | 58 const TargetRegisterClass *RC = local 64 if (RC == &WebAssembly::I32RegClass) 66 else if (RC == &WebAssembly::I64RegClass) 68 else if (RC == &WebAssembly::F32RegClass) 70 else if (RC == &WebAssembly::F64RegClass)
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.h | 71 const TargetRegisterClass *RC, 77 const TargetRegisterClass *RC,
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/external/ltp/testcases/kernel/sched/hyperthreading/ht_enabled/ |
H A D | smt_smp_enabled.sh | 32 RC=0
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | Thumb1RegisterInfo.h | 32 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 62 const TargetRegisterClass *RC,
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H A D | Thumb2InstrInfo.h | 49 const TargetRegisterClass *RC, 55 const TargetRegisterClass *RC,
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaInstrInfo.h | 52 const TargetRegisterClass *RC, 58 const TargetRegisterClass *RC,
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUInstrInfo.h | 56 const TargetRegisterClass *RC, 63 const TargetRegisterClass *RC,
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H A D | SPURegisterInfo.h | 54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC, argument 95 const TargetRegisterClass *RC,
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.h | 64 const TargetRegisterClass *RC, 69 const TargetRegisterClass *RC,
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
H A D | SparcInstrInfo.h | 86 const TargetRegisterClass *RC, 92 const TargetRegisterClass *RC,
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
H A D | XCoreInstrInfo.h | 72 const TargetRegisterClass *RC, 78 const TargetRegisterClass *RC,
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H A D | XCoreFrameLowering.cpp | 296 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local 298 it->getFrameIdx(), RC, TRI); 322 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local 324 RC, TRI); 345 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass; local 354 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true); 356 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), 364 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 365 RC [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ResourcePriorityQueue.cpp | 369 const TargetRegisterClass *RC = *I; local 370 RegBalance += rawRegPressureDelta(SU, RC->getID()); 376 const TargetRegisterClass *RC = *I; local 377 if ((RegPressure[RC->getID()] + 378 rawRegPressureDelta(SU, RC->getID()) > 0) && 379 (RegPressure[RC->getID()] + 380 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) 381 RegBalance += rawRegPressureDelta(SU, RC->getID()); 489 const TargetRegisterClass *RC local 500 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
H A D | BlackfinISelDAGToDAG.cpp | 119 static inline bool isCC(const TargetRegisterClass *RC) { argument 120 return BF::AnyCCRegClass.hasSubClassEq(RC); 123 static inline bool isDCC(const TargetRegisterClass *RC) { argument 124 return BF::DRegClass.hasSubClassEq(RC) || isCC(RC);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 372 const TargetRegisterClass *RC = local 374 if (!RC) 382 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || 383 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { 396 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || 397 AArch64::FPR32RegClass.hasSubClassEq(RC)) { 492 const TargetRegisterClass *RC = nullptr; local 495 RC = &AArch64::GPR64RegClass; 499 RC = &AArch64::GPR32RegClass; 503 RC 2177 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 2281 loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 3280 genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind = FMAInstKind::Default) argument 3345 genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC) argument 3392 const TargetRegisterClass *RC; local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | BitTracker.cpp | 50 // RegisterCell RC = BT.get(Reg); 51 // if (RC[3].is(1)) 106 raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { argument 107 unsigned n = RC.Bits.size(); 117 for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) { 118 const BT::BitValue &V = RC[i]; 119 const BT::BitValue &SV = RC[Start]; 156 OS << "]:" << RC[Start]; local 159 const BT::BitValue &SV = RC[Start]; 186 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigne argument 200 insert(const BT::RegisterCell &RC, const BitMask &M) argument [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 787 // Returns true if RC is a strict subclass. 788 // RC is a sub-class of this class if it is a valid replacement for any 792 // 1. All RC registers are also in this. 793 // 2. The RC spill size must not be smaller than our spill size. 794 // 3. RC spill alignment must be compatible with ours. 855 CodeGenRegisterClass &RC = *I; local 856 RC.SubClasses.resize(RegClasses.size()); 857 RC.SubClasses.set(RC.EnumValue); 859 // Normally, all subclasses have IDs >= rci, unless RC i 1036 addToMaps(CodeGenRegisterClass *RC) argument 1048 getOrCreateSubClass(const CodeGenRegisterClass *RC, const CodeGenRegister::Vec *Members, StringRef Name) argument 1867 inferCommonSubClass(CodeGenRegisterClass *RC) argument 1908 inferSubClassWithSubReg(CodeGenRegisterClass *RC) argument 1952 inferMatchingSuperRegClass(CodeGenRegisterClass *RC, std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) argument 2029 CodeGenRegisterClass *RC = &*I; local [all...] |
H A D | CodeGenRegisters.h | 290 // R:SubRegIndex in this RC for all R in SuperRC. 333 // Returns true if RC is a subclass. 334 // RC is a sub-class of this class if it is a valid replacement for any 338 // 1. All RC registers are also in this. 339 // 2. The RC spill size must not be smaller than our spill size. 340 // 3. RC spill alignment must be compatible with ours. 342 bool hasSubClass(const CodeGenRegisterClass *RC) const { 343 return SubClasses.test(RC->EnumValue); 413 Key(const CodeGenRegisterClass &RC) argument 414 : Members(&RC 535 inferMatchingSuperRegClass(CodeGenRegisterClass *RC) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | RegisterScavenging.cpp | 257 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { 258 for (unsigned Reg : *RC) { 268 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { argument 270 for (unsigned Reg : *RC) 349 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, 355 BitVector Candidates = TRI->getAllocatableSet(MF, RC); 366 BitVector Available = getRegsAvailable(RC); 382 // the requirements of the class RC. 384 unsigned NeedSize = RC->getSize(); 385 unsigned NeedAlign = RC [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); local 155 unsigned VR = MRI.createVirtualRegister(RC); 158 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); 169 const TargetRegisterClass *RC = RegInfo.intRegClass(4); local 170 unsigned VR = MRI.createVirtualRegister(RC); 175 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); 187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); local 188 unsigned VR0 = MRI.createVirtualRegister(RC); 189 unsigned VR1 = MRI.createVirtualRegister(RC); 196 TII.loadRegFromStack(MBB, I, VR0, FI, RC, 212 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); local 244 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); local 293 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 356 const TargetRegisterClass *RC = local 395 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? local 695 const TargetRegisterClass *RC = local 812 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local 869 const TargetRegisterClass *RC = STI.hasMips64() ? local 883 const TargetRegisterClass *RC = local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 46 const TargetRegisterClass *RC, 52 if (RC == &SystemZ::GR32RegClass || 53 RC == &SystemZ::ADDR32RegClass) 55 else if (RC == &SystemZ::GR64RegClass || 56 RC == &SystemZ::ADDR64RegClass) { 58 } else if (RC == &SystemZ::FP32RegClass) { 60 } else if (RC == &SystemZ::FP64RegClass) { 62 } else if (RC == &SystemZ::GR64PRegClass) { 64 } else if (RC == &SystemZ::GR128RegClass) { 76 const TargetRegisterClass *RC, 43 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 73 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/clang/test/CodeGenCXX/ |
H A D | devirtualize-virtual-function-calls-final.cpp | 187 struct RC final : public RA { 202 A *f(RC *x) { 215 A *fop(RC *x) {
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/external/ltp/testcases/network/stress/route/ |
H A D | route6-change-if | 317 RC=0 319 test_body 1 || RC=`expr $RC + 1` # Case of route command 320 test_body 2 || RC=`expr $RC + 1` # Case of ip command 323 exit $RC
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/external/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | RegisterBank.h | 70 /// Check whether this register bank covers \p RC. 72 /// the registers that \p RC contains. 74 bool covers(const TargetRegisterClass &RC) const;
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