Searched refs:ARM_AM (Results 1 - 25 of 35) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMSelectionDAGInfo.h22 namespace ARM_AM { namespace in namespace:llvm
25 default: return ARM_AM::no_shift;
26 case ISD::SHL: return ARM_AM::lsl;
27 case ISD::SRL: return ARM_AM::lsr;
28 case ISD::SRA: return ARM_AM::asr;
29 case ISD::ROTR: return ARM_AM::ror;
33 //case ARMISD::RRX: return ARM_AM::rrx;
36 } // end namespace ARM_AM
H A DARMLoadStoreOptimizer.cpp132 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
139 case ARM_AM::ia: return ARM::LDMIA;
140 case ARM_AM::da: return ARM::LDMDA;
141 case ARM_AM::db: return ARM::LDMDB;
142 case ARM_AM::ib: return ARM::LDMIB;
149 case ARM_AM::ia: return ARM::STMIA;
150 case ARM_AM::da: return ARM::STMDA;
151 case ARM_AM::db: return ARM::STMDB;
152 case ARM_AM::ib: return ARM::STMIB;
160 case ARM_AM
211 namespace ARM_AM { namespace in namespace:llvm
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H A DARMISelDAGToDAG.cpp97 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
184 return ARM_AM::getSOImmVal(Imm) != -1;
188 return ARM_AM::getSOImmVal(~Imm) != -1;
192 return ARM_AM::getT2SOImmVal(Imm) != -1;
196 return ARM_AM::getT2SOImmVal(~Imm) != -1;
380 ARM_AM::ShiftOpc ShOpcVal,
387 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
397 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
401 if (ShOpcVal == ARM_AM
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H A DARMCodeEmitter.cpp401 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
403 case ARM_AM::asr: return 2;
404 case ARM_AM::lsl: return 0;
405 case ARM_AM::lsr: return 1;
406 case ARM_AM::ror:
407 case ARM_AM::rrx: return 3;
723 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
725 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
726 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
927 ARM_AM
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H A DThumb2InstrInfo.cpp186 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
246 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
251 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
253 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
259 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
268 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
270 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
424 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
450 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
455 assert(ARM_AM
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H A DARMBaseInstrInfo.cpp164 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
165 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
167 if (ARM_AM::getSOImmVal(Amt) == -1)
176 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
177 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
190 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
191 unsigned Amt = ARM_AM
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H A DARMBaseRegisterInfo.cpp908 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
909 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
916 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
917 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
923 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
924 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h23 namespace ARM_AM { namespace in namespace:llvm
26 default: return ARM_AM::no_shift;
27 case ISD::SHL: return ARM_AM::lsl;
28 case ISD::SRL: return ARM_AM::lsr;
29 case ISD::SRA: return ARM_AM::asr;
30 case ISD::ROTR: return ARM_AM::ror;
34 //case ARMISD::RRX: return ARM_AM::rrx;
37 } // end namespace ARM_AM
H A DARMLoadStoreOptimizer.cpp207 int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField)
208 : ARM_AM::getAM5Offset(OffField) * 4;
209 ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField)
210 : ARM_AM::getAM5Op(OffField);
212 if (Op == ARM_AM::sub)
226 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) {
233 case ARM_AM::ia: return ARM::LDMIA;
234 case ARM_AM::da: return ARM::LDMDA;
235 case ARM_AM
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H A DARMISelDAGToDAG.cpp89 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
177 return ARM_AM::getSOImmVal(Imm) != -1;
181 return ARM_AM::getSOImmVal(~Imm) != -1;
185 return ARM_AM::getT2SOImmVal(Imm) != -1;
189 return ARM_AM::getT2SOImmVal(~Imm) != -1;
464 ARM_AM::ShiftOpc ShOpcVal,
471 return ShOpcVal == ARM_AM::lsl &&
481 if (ARM_AM::isThumbImmShiftedVal(Val)) return 2; // MOV + LSL
483 if (ARM_AM::getSOImmVal(Val) != -1) return 1; // MOV
484 if (ARM_AM
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H A DARMBaseInstrInfo.cpp160 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
161 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
163 if (ARM_AM::getSOImmVal(Amt) == -1)
175 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
176 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
197 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
198 unsigned Amt = ARM_AM
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H A DThumb2InstrInfo.cpp242 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
307 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
312 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
314 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
320 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
329 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
331 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
492 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
518 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
523 assert(ARM_AM
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H A DARMFastISel.cpp156 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
438 Imm = ARM_AM::getFP64Imm(Val);
441 Imm = ARM_AM::getFP32Imm(Val);
493 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
494 (ARM_AM::getSOImmVal(Imm) != -1);
1379 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1380 (ARM_AM::getSOImmVal(Imm) != -1);
1634 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1635 (ARM_AM::getSOImmVal(Imm) != -1);
2621 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM
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H A DARMBaseRegisterInfo.cpp466 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
467 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
474 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
475 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
481 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
482 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
H A DARMMCInstLower.cpp145 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp65 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
73 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
249 ARM_AM::ShiftOpc ShOpc = ARM_AM
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp167 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
170 case ARM_AM::da: return 0;
171 case ARM_AM::ia: return 1;
172 case ARM_AM::db: return 2;
173 case ARM_AM::ib: return 3;
178 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
181 case ARM_AM::no_shift:
182 case ARM_AM::lsl: return 0;
183 case ARM_AM
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H A DARMAddressingModes.h24 /// ARM_AM - ARM Addressing Mode Stuff
25 namespace ARM_AM { namespace in namespace:llvm
47 case ARM_AM::asr: return "asr";
48 case ARM_AM::lsl: return "lsl";
49 case ARM_AM::lsr: return "lsr";
50 case ARM_AM::ror: return "ror";
51 case ARM_AM::rrx: return "rrx";
58 case ARM_AM::asr: return 2;
59 case ARM_AM::lsl: return 0;
60 case ARM_AM
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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
197 case ARM_AM::da: return 0;
198 case ARM_AM::ia: return 1;
199 case ARM_AM::db: return 2;
200 case ARM_AM::ib: return 3;
205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
207 case ARM_AM::no_shift:
208 case ARM_AM::lsl: return 0;
209 case ARM_AM
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H A DARMAddressingModes.h25 /// ARM_AM - ARM Addressing Mode Stuff
26 namespace ARM_AM { namespace in namespace:llvm
48 case ARM_AM::asr: return "asr";
49 case ARM_AM::lsl: return "lsl";
50 case ARM_AM::lsr: return "lsr";
51 case ARM_AM::ror: return "ror";
52 case ARM_AM::rrx: return "rrx";
59 case ARM_AM::asr: return 2;
60 case ARM_AM::lsl: return 0;
61 case ARM_AM
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/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp44 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
46 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
50 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
53 if (ShOpc != ARM_AM::rrx) {
85 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
96 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
107 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
333 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
343 ARM_AM::ShiftOpc ShiftTy;
352 ARM_AM::ShiftOpc ShiftTy;
358 ARM_AM::ShiftOpc ShiftTy;
643 return ARM_AM::getSOImmVal(Value) != -1;
651 return ARM_AM::getT2SOImmVal(Value) != -1;
675 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
708 if (Memory.ShiftType != ARM_AM::no_shift) return false;
720 return PostIdxReg.ShiftTy == ARM_AM
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/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
515 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
525 ARM_AM::ShiftOpc ShiftTy;
535 ARM_AM::ShiftOpc ShiftTy;
542 ARM_AM::ShiftOpc ShiftTy;
751 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1022 return (ARM_AM::getSOImmVal(Value) != -1 ||
1023 ARM_AM::getSOImmVal(-Value) != -1);
1030 return ARM_AM::getT2SOImmVal(Value) != -1;
1037 return ARM_AM
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1031 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1034 Shift = ARM_AM::lsl;
1037 Shift = ARM_AM::lsr;
1040 Shift = ARM_AM::asr;
1043 Shift = ARM_AM::ror;
1047 if (Shift == ARM_AM::ror && imm == 0)
1048 Shift = ARM_AM::rrx;
1070 ARM_AM::ShiftOpc Shift = ARM_AM
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/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1148 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1151 Shift = ARM_AM::lsl;
1154 Shift = ARM_AM::lsr;
1157 Shift = ARM_AM::asr;
1160 Shift = ARM_AM::ror;
1164 if (Shift == ARM_AM::ror && imm == 0)
1165 Shift = ARM_AM::rrx;
1187 ARM_AM::ShiftOpc Shift = ARM_AM
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