Searched refs:DstRC (Results 1 - 24 of 24) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp143 const TargetRegisterClass *DstRC = local
148 return std::make_pair(SrcRC, DstRC);
152 const TargetRegisterClass *DstRC,
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
158 const TargetRegisterClass *DstRC,
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
193 const TargetRegisterClass *SrcRC, *DstRC; local
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
204 MRI.setRegClass(DstReg, DstRC);
151 isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument
157 isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument
264 const TargetRegisterClass *SrcRC, *DstRC; local
356 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; local
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H A DSILowerI1Copies.cpp102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); local
105 if (DstRC == &AMDGPU::VReg_1RegClass &&
132 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
H A DSIInstrInfo.cpp336 const TargetRegisterClass *DstRC = MRI.getRegClass(FirstDst->getReg()); local
338 return (NumLoads * DstRC->getSize()) <= LoadClusterThreshold;
522 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
524 if (DstRC->getSize() == 4) {
525 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
526 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
528 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
2280 const TargetRegisterClass *DstRC
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H A DSIInstrInfo.h141 // \brief Returns an opcode that can be used to move a value to a \p DstRC
143 // DstRC, then AMDGPU::COPY is returned.
144 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
/external/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp157 const TargetRegisterClass *DstRC,
162 if (DstRC == SrcRC)
187 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
190 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
192 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
193 return !TRI.getCommonSubClass(SrcRC, DstRC);
441 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); local
442 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
490 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); local
491 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, M
155 isCrossCopy(const MachineRegisterInfo &MRI, const MachineInstr &MI, const TargetRegisterClass *DstRC, const MachineOperand &MO) argument
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H A DRegisterCoalescer.cpp353 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); local
361 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
368 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
372 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
375 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
390 CrossClass = NewRC != DstRC || NewRC != SrcRC;
971 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
973 TRI->getCommonSubClass(DefRC, DstRC);
1354 auto DstRC = MRI->getRegClass(CP.getDstReg()); local
1359 std::swap(SrcRC, DstRC);
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H A DPeepholeOptimizer.cpp428 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
429 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
430 if (!DstRC)
536 MRI->constrainRegClass(DstReg, DstRC);
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp137 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; local
142 DstRC = MRI->getRegClass(VRBase);
145 DstRC = UseRC;
147 DstRC = TLI->getRegClassFor(VT);
156 VRBase = MRI->createVirtualRegister(DstRC);
294 const TargetRegisterClass *DstRC = 0;
296 DstRC = TII->getRegClass(*II, IIOpNum, TRI);
297 assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
299 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSiz
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/external/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp131 const TargetRegisterClass *DstRC = local
141 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
H A DPPCVSXSwapRemoval.cpp886 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
887 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
900 if (DstRC == &PPC::VRRCRegClass) {
/external/llvm/utils/TableGen/
H A DFastISelEmitter.cpp193 const CodeGenRegisterClass *DstRC = nullptr;
275 if (DstRC) {
276 if (DstRC != RC && !DstRC->hasSubClass(RC))
279 DstRC = RC;
479 const CodeGenRegisterClass *DstRC = nullptr;
487 DstRC = &Target.getRegisterClass(Op0Rec);
488 if (!DstRC)
527 DstRC))
578 DstRC,
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp157 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; local
162 DstRC = MRI->getRegClass(VRBase);
165 DstRC = UseRC;
167 DstRC = TLI->getRegClassFor(VT);
176 VRBase = MRI->createVirtualRegister(DstRC);
333 const TargetRegisterClass *DstRC = nullptr;
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
336 assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) &&
338 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSiz
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXInstrInfo.h48 const TargetRegisterClass *DstRC,
H A DPTXInstrInfo.cpp72 const TargetRegisterClass *DstRC,
75 if (DstRC != SrcRC)
79 if (DstRC == map[i].cls) {
69 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg, const TargetRegisterClass *DstRC, const TargetRegisterClass *SrcRC, DebugLoc DL) const argument
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DFastISelEmitter.cpp186 const CodeGenRegisterClass *DstRC = 0;
266 if (DstRC) {
267 if (DstRC != RC && !DstRC->hasSubClass(RC))
270 DstRC = RC;
455 const CodeGenRegisterClass *DstRC = 0;
463 DstRC = &Target.getRegisterClass(Op0Rec);
464 if (!DstRC)
542 DstRC,
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h189 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
193 const TargetRegisterClass *DstRC,
H A DARMBaseRegisterInfo.cpp786 const TargetRegisterClass *DstRC,
797 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
805 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
783 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const argument
H A DARMFastISel.cpp2036 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); local
2037 unsigned ResultReg = createResultReg(DstRC);
2056 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); local
2058 unsigned ResultReg = createResultReg(DstRC);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DRegisterCoalescer.cpp157 const TargetRegisterClass *DstRC,
290 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); local
291 if (!TRI.getCommonSubClass(DstRC, SrcRC))
307 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); local
309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
314 CrossClass = NewRC != DstRC || NewRC != SrcRC;
1104 const TargetRegisterClass *DstRC,
1140 if (DstRC != NewRC && DstSize > ThresSize) {
1141 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
1101 isWinToJoinCrossClass(unsigned SrcReg, unsigned DstReg, const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const TargetRegisterClass *NewRC) argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp639 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);
643 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC))
646 if (DstRC != SrcRC)
648 if (DstRC == InsRC)
651 if (DstRC == &Hexagon::DoubleRegsRegClass)
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h918 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
922 const TargetRegisterClass *DstRC,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMFastISel.cpp1688 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); local
1689 unsigned ResultReg = createResultReg(DstRC);
1703 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); local
1705 unsigned ResultReg = createResultReg(DstRC);
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86InstrInfo.cpp2994 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI); local
2999 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3066 const TargetRegisterClass *DstRC = 0; local
3068 DstRC = getRegClass(MCID, 0, &RI);
3069 VTs.push_back(*DstRC->vt_begin());
3100 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp6474 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); local
6477 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6545 const TargetRegisterClass *DstRC = nullptr; local
6547 DstRC = getRegClass(MCID, 0, &RI, MF);
6548 VTs.push_back(*DstRC->vt_begin());
6581 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),

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