Searched refs:EntrySU (Results 1 - 16 of 16) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGVLIW.cpp173 releaseSuccessors(&EntrySU);
H A DScheduleDAGFast.cpp154 // to be scheduled. Ignore the special EntrySU node.
155 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
H A DScheduleDAGRRList.cpp385 // to be scheduled. Ignore the special EntrySU node.
386 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DScheduleDAGList.cpp162 ReleaseSuccessors(&EntrySU);
H A DScheduleDAGFast.cpp148 // to be scheduled. Ignore the special EntrySU node.
149 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
H A DScheduleDAGRRList.cpp386 // to be scheduled. Ignore the special EntrySU node.
387 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
1367 ReleaseSuccessors(&EntrySU);
/external/llvm/lib/CodeGen/
H A DScheduleDAG.cpp41 MRI(mf.getRegInfo()), EntrySU(), ExitSU() {
52 EntrySU = SUnit();
H A DPostRASchedulerList.cpp538 ReleaseSuccessors(&EntrySU);
H A DScheduleDAGInstrs.cpp1380 if (SU == &EntrySU)
H A DMachineScheduler.cpp616 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
786 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
801 releaseSuccessors(&EntrySU);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DPostRASchedulerList.cpp324 EntrySU = SUnit();
603 ReleaseSuccessors(&EntrySU);
H A DScheduleDAG.cpp39 EntrySU(), ExitSU() {
73 EntrySU = SUnit();
H A DScheduleDAGInstrs.cpp650 if (SU == &EntrySU)
/external/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.h453 SUnit& getEntrySU() { return EntrySU; };
/external/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h584 SUnit EntrySU; // Special node for the region entry. member in class:llvm::SUnit::ScheduleDAG
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DScheduleDAG.h497 SUnit EntrySU; // Special node for the region entry. member in class:llvm::ScheduleDAG

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