/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 62 const MCOperand &MO2 = MI->getOperand(2); local 72 O << ", " << getRegisterName(MO2.getReg()); 82 const MCOperand &MO2 = MI->getOperand(2); local 84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); 243 const MCOperand &MO2 = MI->getOperand(OpNum+1); local 254 O << ' ' << getRegisterName(MO2.getReg()); 261 const MCOperand &MO2 = MI->getOperand(OpNum+1); local 266 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2 281 const MCOperand &MO2 = MI->getOperand(Op+1); local 309 const MCOperand &MO2 = MI->getOperand(Op+1); local 334 const MCOperand &MO2 = MI->getOperand(Op+1); local 342 const MCOperand &MO2 = MI->getOperand(Op+1); local 370 const MCOperand &MO2 = MI->getOperand(OpNum+1); local 396 const MCOperand &MO2 = MI->getOperand(Op+1); local 416 const MCOperand &MO2 = MI->getOperand(Op+1); local 450 const MCOperand &MO2 = MI->getOperand(OpNum+1); local 475 const MCOperand &MO2 = MI->getOperand(OpNum+1); local 499 const MCOperand &MO2 = MI->getOperand(OpNum+1); local 521 const MCOperand &MO2 = MI->getOperand(OpNum+1); local 762 const MCOperand &MO2 = MI->getOperand(Op + 1); local 780 const MCOperand &MO2 = MI->getOperand(Op + 1); local 823 const MCOperand &MO2 = MI->getOperand(OpNum+1); local 839 const MCOperand &MO2 = MI->getOperand(OpNum+1); local [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 82 const MCOperand &MO2 = MI->getOperand(2); local 95 printRegName(O, MO2.getReg()); 105 const MCOperand &MO2 = MI->getOperand(2); local 107 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); 116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { 122 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); 346 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 358 printRegName(O, MO2.getReg()); 366 const MCOperand &MO2 = MI->getOperand(OpNum + 1); 371 printRegImmShift(O, ARM_AM::getSORegShOp(MO2 [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86OptimizeLEAs.cpp | 56 const MachineOperand &MO2); 61 const MachineOperand &MO2); 182 const MachineOperand &MO2) { 183 return MO1.isIdenticalTo(MO2) && 196 const MachineOperand &MO2) { 197 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && 199 return (MO1.isImm() && MO2.isImm()) || 200 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || 201 (MO1.isJTI() && MO2 181 isIdenticalOp(const MachineOperand &MO1, const MachineOperand &MO2) argument 195 isSimilarDispOp(const MachineOperand &MO1, const MachineOperand &MO2) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 691 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); local 693 unsigned Rm = getARMRegisterNumbering(MO2.getReg()); 895 const MCOperand &MO2 = MI.getOperand(OpIdx+2); local 898 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 899 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 900 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 995 const MCOperand &MO2 = MI.getOperand(OpIdx+2); local 997 unsigned Imm = MO2.getImm(); 1100 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); local 1101 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2 1183 const MCOperand &MO2 = MI.getOperand(OpNum+1); local 1201 const MCOperand &MO2 = MI.getOperand(OpNum+1); local [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 864 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); local 866 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1071 const MCOperand &MO2 = MI.getOperand(OpIdx+2); local 1074 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1075 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1076 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1165 const MCOperand &MO2 = MI.getOperand(OpIdx+2); local 1180 unsigned Imm = MO2.getImm(); 1328 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); local 1329 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2 [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 926 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); local 927 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 968 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 973 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 1145 const MachineOperand &MO2 = MI.getOperand(OpIdx); local 1152 if (!MO2.getReg()) { // is immediate 1162 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1164 Binary |= getARMRegisterNumbering(MO2.getReg()); 1216 const MachineOperand &MO2 = MI.getOperand(OpIdx); local 1226 if (MO2 [all...] |
H A D | ARMAsmPrinter.cpp | 907 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id local 914 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); 951 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id local 963 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 402 MCOperand &MO2 = MappedInst.getOperand(2); local 403 MCExpr const *Expr = MO2.getExpr();
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/external/llvm/lib/CodeGen/ |
H A D | ScheduleDAGInstrs.cpp | 706 for (const MachineOperand &MO2 : MI->operands()) { 707 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
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/external/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1461 MCOperand &MO1, MCOperand &MO2) { 1466 TmpInst.addOperand(MO2); 1809 MCOperand &MO2 = Inst.getOperand(2); local 1811 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { 1816 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); 1830 MCOperand &MO2 = Inst.getOperand(2); local 1831 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); 1460 makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, MCOperand &MO2) argument
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/external/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 964 MachineOperand &MO2 = Cond[2]; 965 switch (MO2.getReg()) { 967 MO2.setReg(AMDGPU::PRED_SEL_ONE); 970 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | LiveIntervalAnalysis.cpp | 315 MachineOperand &MO2 = mi->getOperand(i); local 316 if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg()) 317 MO2.setIsUndef();
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