Searched refs:Op2 (Results 1 - 25 of 106) sorted by relevance

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/external/v8/tools/clang/rewrite_to_chrome_style/tests/
H A Doperators-expected.cc11 struct Op2 {}; struct in namespace:blink
13 inline bool operator==(const Op2&, const Op2) { argument
23 blink::Op2 a2, b2;
H A Doperators-original.cc11 struct Op2 {}; struct in namespace:blink
13 inline bool operator==(const Op2&, const Op2) { argument
23 blink::Op2 a2, b2;
/external/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp145 const MCOperand Op2 = Inst.getOperand(2); local
148 ((Op2.isImm() && Op2.getImm() != 0) ||
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
157 (Op2.isReg() && Op2
193 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local
225 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local
264 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local
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/external/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
99 Ops[5].getAsInteger(10, Op2);
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
111 uint32_t Op2 = Bits & 0x7; local
114 utostr(CRm) + "_" + utostr(Op2);
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
347 unsigned Op1, Op2; local
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
360 unsigned Op1, Op2; local
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
366 DecodeGRRegsRegisterClass(Inst, Op2, Addres
373 unsigned Op1, Op2; local
386 unsigned Op1, Op2; local
400 unsigned Op1, Op2; local
413 unsigned Op1, Op2; local
426 unsigned Op1, Op2; local
511 unsigned Op1, Op2; local
525 unsigned Op1, Op2; local
539 unsigned Op1, Op2, Op3; local
552 unsigned Op1, Op2, Op3; local
565 unsigned Op1, Op2, Op3; local
578 unsigned Op1, Op2, Op3; local
591 unsigned Op1, Op2, Op3; local
605 unsigned Op1, Op2, Op3; local
620 unsigned Op1, Op2, Op3; local
634 unsigned Op1, Op2, Op3; local
648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
682 unsigned Op1, Op2, Op3, Op4, Op5; local
702 unsigned Op1, Op2, Op3; local
721 unsigned Op1, Op2, Op3; local
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/external/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.h26 SDValue Chain, SDValue Op1, SDValue Op2,
/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetSelectionDAGInfo.h59 SDValue Op1, SDValue Op2,
76 SDValue Op1, SDValue Op2,
92 SDValue Op1, SDValue Op2,
57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
74 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
90 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
/external/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/
H A DNaClBitCodes.h225 const NaClBitCodeAbbrevOp &Op2) {
226 return Op1.Compare(Op2) < 0;
230 const NaClBitCodeAbbrevOp &Op2) {
231 return Op1.Compare(Op2) <= 0;
235 const NaClBitCodeAbbrevOp &Op2) {
236 return Op1.Compare(Op2) == 0;
240 const NaClBitCodeAbbrevOp &Op2) {
241 return Op1.Compare(Op2) != 0;
245 const NaClBitCodeAbbrevOp &Op2) {
246 return Op1.Compare(Op2) >
224 operator <(const NaClBitCodeAbbrevOp &Op1, const NaClBitCodeAbbrevOp &Op2) argument
229 operator <=(const NaClBitCodeAbbrevOp &Op1, const NaClBitCodeAbbrevOp &Op2) argument
234 operator ==(const NaClBitCodeAbbrevOp &Op1, const NaClBitCodeAbbrevOp &Op2) argument
239 operator !=(const NaClBitCodeAbbrevOp &Op1, const NaClBitCodeAbbrevOp &Op2) argument
244 operator >=(const NaClBitCodeAbbrevOp &Op1, const NaClBitCodeAbbrevOp &Op2) argument
249 operator >(const NaClBitCodeAbbrevOp &Op1, const NaClBitCodeAbbrevOp &Op2) argument
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/external/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { argument
171 if (Op1.getType() != Op2.getType())
176 return Op1.getReg() == Op2.getReg();
178 return Op1.getImm() == Op2.getImm();
295 MachineOperand &Op2 = AluIter->getOperand(2); local
302 if (Op2.isImm()) {
313 // Check that the Op2 would fit in the immediate field of the
315 ((IsSpls && isInt<10>(Op2.getImm())) ||
316 (!IsSpls && isInt<16>(Op2.getImm())))) ||
317 Offset.getImm() == Op2
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/external/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h51 SDValue Op2, SDValue Op3,
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile,
80 SDValue Op2, SDValue Op3,
92 SDValue Op1, SDValue Op2, SDValue Op3,
129 SDValue Op1, SDValue Op2,
49 EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
65 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
78 EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
91 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
128 EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
H A DSelectionDAG.h733 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument
739 Ops.push_back(Op2);
1002 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
1003 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1005 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1007 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1018 SDValue Op1, SDValue Op2);
1020 SDValue Op1, SDValue Op2, SDValue Op3);
1033 EVT VT2, SDValue Op1, SDValue Op2);
1035 EVT VT2, SDValue Op1, SDValue Op2, SDValu
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMSelectionDAGInfo.h60 SDValue Op1, SDValue Op2,
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXSelectionDAGInfo.h44 SDValue Op1, SDValue Op2,
/external/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp162 MCOperand Op2 = MI.getOperand(2); local
163 assert(Op2.isImm() && "Second operand is not immediate.");
164 Encoding |= Op2.getImm() & 0xffff;
/external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/
H A DPTXInstPrinter.cpp143 const MCOperand &Op2 = MI->getOperand(OpNo+1); local
145 if (Op2.getImm() == 0)
147 O << "+" << Op2.getImm();
/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp816 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local
817 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
821 delete &Op2;
829 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local
830 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
834 delete &Op2;
843 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; local
844 if (isSrcOp(Op) && isDstOp(Op2)) {
848 delete &Op2;
856 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); local
886 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); local
[all...]
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h57 SDValue Chain, SDValue Op1, SDValue Op2,
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DSelectionDAG.h484 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument
490 Ops.push_back(Op2);
708 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
709 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
711 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
713 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
725 SDValue Op1, SDValue Op2);
727 SDValue Op1, SDValue Op2, SDValue Op3);
741 EVT VT2, SDValue Op1, SDValue Op2);
743 EVT VT2, SDValue Op1, SDValue Op2, SDValu
[all...]
H A DISDOpcodes.h782 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
788 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp273 SDValue Op2 = Op.getOperand(2); local
288 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
295 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
296 return DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
/external/llvm/lib/IR/
H A DProfileSummary.cpp134 ConstantAsMetadata *Op2 = local
137 if (!Op0 || !Op1 || !Op2)
141 cast<ConstantInt>(Op2->getValue())->getZExtValue());
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp151 const auto &Op2 = MI.getOperand(2); local
152 if (!Op2.isReg())
157 unsigned NewReg = Op2.getReg();
/external/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp688 MachineOperand &Op2 = MI->getOperand(2); local
706 if (Op2.isImm()) {
708 .addImm(Op2.getImm());
709 } else if (Op2.isReg()) {
711 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
742 MachineOperand &Op2 = MI->getOperand(2); local
743 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
744 int64_t Sh64 = Op2
866 MachineOperand &Op2 = MI->getOperand(2); local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp718 SDValue Op2 = Op.getOperand(2); local
721 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
755 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
762 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
763 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
938 SDValue Op2 = Op.getOperand(2); local
966 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
[all...]
/external/llvm/include/llvm/Transforms/Utils/
H A DBuildLibCalls.h90 /// function is known to take type matching 'Op1' and 'Op2' and return one
91 /// value with the same type. If 'Op1/Op2' are long double, 'l' is added as
92 /// the suffix of name, if 'Op1/Op2' are float, we add a 'f' suffix.
93 Value *emitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name,

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