Searched refs:Outs (Results 1 - 25 of 86) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
H A DPPCCCState.cpp18 const SmallVectorImpl<ISD::OutputArg> &Outs) {
19 for (const auto &I : Outs) {
17 PreAnalyzeCallOperands( const SmallVectorImpl<ISD::OutputArg> &Outs) argument
H A DPPCCCState.h23 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
/external/llvm/lib/Target/Mips/
H A DMipsCCState.h38 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
43 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
73 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
77 PreAnalyzeCallOperands(Outs, FuncArgs, CallNode);
78 CCState::AnalyzeCallOperands(Outs, Fn);
87 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
110 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
112 PreAnalyzeReturnForF128(Outs);
113 CCState::AnalyzeReturn(Outs, F
[all...]
H A DMipsCCState.cpp87 const SmallVectorImpl<ISD::OutputArg> &Outs) {
89 for (unsigned i = 0; i < Outs.size(); ++i) {
100 const SmallVectorImpl<ISD::OutputArg> &Outs,
103 for (unsigned i = 0; i < Outs.size(); ++i) {
105 originalTypeIsF128(FuncArgs[Outs[i].OrigArgIndex].Ty, CallNode));
107 FuncArgs[Outs[i].OrigArgIndex].Ty->isFloatingPointTy());
108 CallOperandIsFixed.push_back(Outs[i].IsFixed);
86 PreAnalyzeReturnForF128( const SmallVectorImpl<ISD::OutputArg> &Outs) argument
99 PreAnalyzeCallOperands( const SmallVectorImpl<ISD::OutputArg> &Outs, std::vector<TargetLowering::ArgListEntry> &FuncArgs, const SDNode *CallNode) argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h59 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
63 for (unsigned i = 0; i < Outs.size(); ++i)
64 ArgIsFixed.push_back(Outs[i].IsFixed);
67 for (unsigned i = 0; i < Outs.size(); ++i)
68 ArgIsShortVector.push_back(IsShortVectorType(Outs[i].ArgVT));
70 CCState::AnalyzeCallOperands(Outs, Fn);
75 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DCallingConvLower.cpp88 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
91 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
92 MVT VT = Outs[i].VT;
93 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
102 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
105 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
106 MVT VT = Outs[i].VT;
107 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
120 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
122 unsigned NumOps = Outs
[all...]
/external/llvm/lib/CodeGen/
H A DCallingConvLower.cpp89 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
92 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
93 MVT VT = Outs[i].VT;
94 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
103 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
106 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
107 MVT VT = Outs[i].VT;
108 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
121 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument
123 unsigned NumOps = Outs
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
H A DBlackfinISelLowering.h68 const SmallVectorImpl<ISD::OutputArg> &Outs,
77 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXISelLowering.h61 const SmallVectorImpl<ISD::OutputArg> &Outs,
70 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DPTXISelLowering.cpp261 const SmallVectorImpl<ISD::OutputArg> &Outs,
271 assert(Outs.size() == 0 && "Kernel must return void.");
274 assert(Outs.size() <= 1 && "Can at most return one value.");
286 assert(Outs.size() < 2 && "Device functions can return at most one value");
288 if (Outs.size() == 1) {
298 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
299 EVT RegVT = Outs[i].VT;
348 const SmallVectorImpl<ISD::OutputArg> &Outs,
362 // The layout of the ops will be [Chain, #Ins, Ins, Callee, #Outs, Outs]
258 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
345 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
H A DSparcISelLowering.h83 const SmallVectorImpl<ISD::OutputArg> &Outs,
92 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
H A DSystemZISelLowering.h97 const SmallVectorImpl<ISD::OutputArg> &Outs,
126 const SmallVectorImpl<ISD::OutputArg> &Outs,
135 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h67 const SmallVectorImpl<ISD::OutputArg> &Outs,
70 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DWebAssemblyISelLowering.cpp308 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local
310 for (unsigned i = 0; i < Outs.size(); ++i) {
311 const ISD::OutputArg &Out = Outs[i];
435 const SmallVectorImpl<ISD::OutputArg> &Outs,
438 return Outs.size() <= 1;
443 const SmallVectorImpl<ISD::OutputArg> &Outs,
446 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
455 for (const ISD::OutputArg &Out : Outs) {
433 CanLowerReturn( CallingConv::ID , MachineFunction & , bool , const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext & ) const argument
441 LowerReturn( SDValue Chain, CallingConv::ID CallConv, bool , const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, SelectionDAG &DAG) const argument
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
H A DAlphaISelLowering.h127 const SmallVectorImpl<ISD::OutputArg> &Outs,
136 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h112 const SmallVectorImpl<ISD::OutputArg> &Outs,
140 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h134 const SmallVectorImpl<ISD::OutputArg> &Outs,
162 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUISelLowering.h166 const SmallVectorImpl<ISD::OutputArg> &Outs,
175 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
H A DMBlazeISelLowering.h138 const SmallVectorImpl<ISD::OutputArg> &Outs,
147 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsISelLowering.h153 const SmallVectorImpl<ISD::OutputArg> &Outs,
162 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/BPF/
H A DBPFISelLowering.h76 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h155 const SmallVectorImpl<ISD::OutputArg> &Outs,
160 const SmallVectorImpl<ISD::OutputArg> &Outs,
165 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
H A DMSP430ISelLowering.h128 const SmallVectorImpl<ISD::OutputArg> &Outs,
157 const SmallVectorImpl<ISD::OutputArg> &Outs,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
H A DXCoreISelLowering.h120 const SmallVectorImpl<ISD::OutputArg> &Outs,
181 const SmallVectorImpl<ISD::OutputArg> &Outs,
190 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCISelLowering.h442 const SmallVectorImpl<ISD::OutputArg> &Outs,
451 const SmallVectorImpl<ISD::OutputArg> &Outs,
457 const SmallVectorImpl<ISD::OutputArg> &Outs,
477 const SmallVectorImpl<ISD::OutputArg> &Outs,
485 const SmallVectorImpl<ISD::OutputArg> &Outs,

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