/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | DeadMachineInstructionElim.cpp | 71 if (MO.isReg() && MO.isDef()) { 136 if (!MO.isReg() || !MO.isDef()) 165 if (MO.isReg() && MO.isDef()) {
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H A D | LiveRangeEdit.cpp | 90 if (!MO.isReg() || !MO.getReg() || MO.isDef()) 174 if (MO.isDef()) { 256 (MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) || 261 if (MOI->isDef()) {
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H A D | MachineLICM.cpp | 413 if (!MO.isDef()) { 516 if (!MO.isReg() || MO.isDef() || !MO.getReg()) 546 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; 713 if (MO.isDef()) 743 if (MO.isDef()) 915 if (!DefMO.isReg() || !DefMO.isDef()) 970 if (MO.isDef()) { 1031 if (MO.isDef()) { 1079 if (!MO.isReg() || !MO.isDef()) 1192 if (MO.isReg() && MO.isDef() [all...] |
H A D | MachineInstr.cpp | 69 if (*Head && (*Head)->isDef()) 155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, argument 176 IsDef = isDef; 196 return getReg() == Other.getReg() && isDef() == Other.isDef() && 242 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 246 if (isDef()) { 759 if (MO.isDef()) { 951 if (!MO.isReg() || !MO.isDef()) 995 if (!MO.isReg() || !MO.isDef() || M [all...] |
H A D | ProcessImplicitDefs.cpp | 143 if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef()) 170 if (MO.isDef()) { 191 if (!MO.isReg() || !MO.isDef())
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H A D | RegisterScavenging.cpp | 171 assert(MO.isDef()); 214 assert(MO.isDef()); 292 if (MO.isDef())
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H A D | PeepholeOptimizer.cpp | 283 if (MO.isDef()) 305 if (!MO.isReg() || MO.isDef()) 310 if (!MO.isDef()) { 378 if (!MO.isReg() || MO.isDef())
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64DeadRegisterDefinitionsPass.cpp | 72 if (MO.isReg() && MO.isDef()) 104 if (MO.isReg() && MO.isDead() && MO.isDef()) {
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/external/llvm/lib/CodeGen/ |
H A D | ImplicitNullChecks.cpp | 207 if (MO.isDef()) { 266 assert((!MO.isDef() || RegDefs.count(MO.getReg())) && 268 return !MO.isDef() || RegDefs.find(MO.getReg())->second == MI; 282 if (MO.isDef()) 436 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) 542 if (!MO.isReg() || !MO.isDef()) 552 if (!MO.isReg() || !MO.getReg() || !MO.isDef())
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H A D | LiveRangeCalc.cpp | 62 if (!MO.isDef() && !MO.readsReg()) 93 if (MO.isDef()) 100 if (MO.isDef()) 107 if (MO.isDef() && !LI.hasSubRanges()) 188 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); 196 if (MO.isDef())
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H A D | DeadMachineInstructionElim.cpp | 79 if (MO.isReg() && MO.isDef()) { 145 if (MO.isReg() && MO.isDef()) {
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H A D | LivePhysRegs.cpp | 49 if (!O->isDef()) 82 if (O->isDef()) {
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H A D | MachineInstrBundle.cpp | 141 if (MO.isDef()) { 280 if (MO.isDef()) 285 if (MO.isDef()) 327 } else if (MO.isDef()) {
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H A D | MachineLICM.cpp | 386 if (!MO.isDef()) { 505 if (!MO.isReg() || MO.isDef() || !MO.getReg()) 531 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; 719 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) 814 if (MO.isDef()) 937 if (!MO.isReg() || !MO.isDef()) 1006 if (!DefMO.isReg() || !DefMO.isDef()) 1101 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) { 1254 if (MO.isReg() && MO.isDef() && 1346 if (MO.isReg() && MO.isDef() [all...] |
H A D | LiveRangeEdit.cpp | 171 if (MO.isDef()) { 289 else if (MOI->isDef()) 299 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) || 304 if (MOI->isDef()) {
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H A D | RenameIndependentSubregs.cpp | 180 if (!MO.isDef() && !MO.readsReg()) 190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) 219 if (!MO.isDef() && !MO.readsReg()) 334 if (!MO.isDef())
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H A D | VirtRegMap.cpp | 411 if (MO.readsReg() && (MO.isDef() || MO.isKill())) 414 if (MO.isDef()) { 429 assert(MO.isDef()); 437 if (MO.isDef())
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 282 bool isDef() const { function in class:llvm::MachineOperand 580 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 606 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, 613 assert(!(isDead && !isDef) && "Dead flag on non-def"); 614 assert(!(isKill && isDef) && "Kill flag on def"); 616 Op.IsDef = isDef;
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SIInsertWaits.cpp | 231 if (Op.isDef()) 346 if (Op.isDef()) 475 if (Op.isDef()) { 507 if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0)
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 236 bool isDef() const { function in class:llvm::MachineOperand 463 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 489 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, argument 496 Op.IsDef = isDef;
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H A D | MachineRegisterInfo.h | 354 (!ReturnDefs && op->isDef()) || 386 (!ReturnDefs && Op->isDef()) ||
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DbgValueHistoryCalculator.cpp | 167 if (MO.isReg() && MO.isDef() && MO.getReg()) { 194 if (MO.isReg() && MO.isDef() && MO.getReg()) {
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/external/llvm/lib/Target/Lanai/ |
H A D | LanaiDelaySlotFiller.cpp | 212 if (MO.isDef()) { 241 if (MO.isDef())
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
H A D | MBlazeDelaySlotFiller.cpp | 140 bool aop_is_def = a->getOperand(aop).isDef(); 148 bool mop_is_def = m->getOperand(mop).isDef();
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 204 if (MO.isDef()) { 238 if (MO.isDef())
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