| /external/clang/test/CodeGen/ |
| H A D | systemz-abi-vector.c | 36 typedef __attribute__((vector_size(32))) char v32i8; typedef
62 v32i8 pass_v32i8(v32i8 arg) { return arg; }
158 struct agg_v32i8 { v32i8 a; };
349 v32i8 va_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, v32i8); }
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 58 v32i8 = 16, // 32 x i8 enumerator in enum:llvm::MVT::SimpleValueType
194 case v32i8: return i8;
218 case v32i8: return 32;
278 case v32i8:
343 if (NumElements == 32) return MVT::v32i8;
504 return (V == MVT::v8f32 || V == MVT::v4f64 || V == MVT::v32i8 ||
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineValueType.h | 73 v32i8 = 26, // 32 x i8
258 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 ||
330 case v32i8:
385 case v32i8:
490 case v32i8:
608 if (NumElements == 32) return MVT::v32i8;
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 191 { ISD::SHL, MVT::v32i8, 2 },
192 { ISD::SRL, MVT::v32i8, 4 },
193 { ISD::SRA, MVT::v32i8, 4 },
212 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence.
215 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence.
218 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence.
224 { ISD::SDIV, MVT::v32i8, 32*20 },
228 { ISD::UDIV, MVT::v32i8, 32*20 },
247 { ISD::SHL, MVT::v32i8, 2 }, // psllw.
256 { ISD::SRL, MVT::v32i8,
[all...] |
| H A D | X86ISelLowering.cpp | 934 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
942 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
949 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
982 for (auto VT : { MVT::v32i8, MVT::v16i16 }) {
988 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1009 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1011 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1018 for (auto VT : { MVT::v32i8, MVT::v16i16 })
1031 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1039 setOperationAction(ISD::MUL, MVT::v32i8, Custo
[all...] |
| H A D | X86FastISel.cpp | 449 case MVT::v32i8:
597 case MVT::v32i8:
|
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| H A D | ValueTypes.cpp | 124 case MVT::v32i8: return "v32i8";
171 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32);
|
| /external/llvm/lib/IR/ |
| H A D | ValueTypes.cpp | 158 case MVT::v32i8: return "v32i8";
236 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32);
|
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 86 case MVT::v32i8: return "MVT::v32i8";
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 73 case MVT::v32i8: return "MVT::v32i8";
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86GenDAGISel.inc | 5806 /*12756*/ OPC_CheckChild1Type, MVT::v32i8,
5817 // Src: (st VR256:v32i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore256>> - Complexity = 22
5818 // Dst: (VMOVAPSYmr addr:iPTR:$dst, VR256:v32i8:$src)
5825 // Src: (st VR256:v32i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 22
5826 // Dst: (VMOVUPSYmr addr:iPTR:$dst, VR256:v32i8:$src)
[all...] |
| H A D | X86ISelLowering.cpp | 975 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1008 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1014 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1019 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1024 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1041 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1046 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1051 // Don't lower v32i8 because there is no 128-bit byte mul
1076 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1077 for (unsigned i = (unsigned)MVT::v32i8;
[all...] |
| H A D | X86GenFastISel.inc | 4024 if (RetVT.SimpleTy != MVT::v32i8)
4061 case MVT::v32i8: return FastEmit_X86ISD_VPERM2F128_MVT_v32i8_rri(RetVT, Op0, Op0IsKill, Op1, Op1IsKill, imm2);
|
| H A D | X86GenRegisterInfo.inc | 2720 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::v8f32, MVT::v4f64, MVT::Other
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 192 LocVT == MVT::v32i8) {
257 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) {
|