1//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the interface of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
18#define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
19
20#include "CodeGenTarget.h"
21#include "X86DisassemblerTables.h"
22#include "llvm/Support/DataTypes.h"
23#include "llvm/TableGen/Record.h"
24
25namespace llvm {
26
27namespace X86Disassembler {
28
29/// RecognizableInstr - Encapsulates all information required to decode a single
30///   instruction, as extracted from the LLVM instruction tables.  Has methods
31///   to interpret the information available in the LLVM tables, and to emit the
32///   instruction into DisassemblerTables.
33class RecognizableInstr {
34private:
35  /// The opcode of the instruction, as used in an MCInst
36  InstrUID UID;
37  /// The record from the .td files corresponding to this instruction
38  const Record* Rec;
39  /// The OpPrefix field from the record
40  uint8_t OpPrefix;
41  /// The OpMap field from the record
42  uint8_t OpMap;
43  /// The opcode field from the record; this is the opcode used in the Intel
44  /// encoding and therefore distinct from the UID
45  uint8_t Opcode;
46  /// The form field from the record
47  uint8_t Form;
48  // The encoding field from the record
49  uint8_t Encoding;
50  /// The OpSize field from the record
51  uint8_t OpSize;
52  /// The AdSize field from the record
53  uint8_t AdSize;
54  /// The hasREX_WPrefix field from the record
55  bool HasREX_WPrefix;
56  /// The hasVEX_4V field from the record
57  bool HasVEX_4V;
58  /// The hasVEX_4VOp3 field from the record
59  bool HasVEX_4VOp3;
60  /// The hasVEX_WPrefix field from the record
61  bool HasVEX_WPrefix;
62  /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
63  bool HasVEX_LPrefix;
64  /// The hasMemOp4Prefix field from the record
65  bool HasMemOp4Prefix;
66  /// The ignoreVEX_L field from the record
67  bool IgnoresVEX_L;
68  /// The hasEVEX_L2Prefix field from the record
69  bool HasEVEX_L2Prefix;
70  /// The hasEVEX_K field from the record
71  bool HasEVEX_K;
72  /// The hasEVEX_KZ field from the record
73  bool HasEVEX_KZ;
74  /// The hasEVEX_B field from the record
75  bool HasEVEX_B;
76  /// The isCodeGenOnly field from the record
77  bool IsCodeGenOnly;
78  /// The ForceDisassemble field from the record
79  bool ForceDisassemble;
80  // The CD8_Scale field from the record
81  uint8_t CD8_Scale;
82  // Whether the instruction has the predicate "In64BitMode"
83  bool Is64Bit;
84  // Whether the instruction has the predicate "In32BitMode"
85  bool Is32Bit;
86
87  /// The instruction name as listed in the tables
88  std::string Name;
89
90  /// Indicates whether the instruction should be emitted into the decode
91  /// tables; regardless, it will be emitted into the instruction info table
92  bool ShouldBeEmitted;
93
94  /// The operands of the instruction, as listed in the CodeGenInstruction.
95  /// They are not one-to-one with operands listed in the MCInst; for example,
96  /// memory operands expand to 5 operands in the MCInst
97  const std::vector<CGIOperandList::OperandInfo>* Operands;
98
99  /// The description of the instruction that is emitted into the instruction
100  /// info table
101  InstructionSpecifier* Spec;
102
103  /// insnContext - Returns the primary context in which the instruction is
104  ///   valid.
105  ///
106  /// @return - The context in which the instruction is valid.
107  InstructionContext insnContext() const;
108
109  /// typeFromString - Translates an operand type from the string provided in
110  ///   the LLVM tables to an OperandType for use in the operand specifier.
111  ///
112  /// @param s              - The string, as extracted by calling Rec->getName()
113  ///                         on a CodeGenInstruction::OperandInfo.
114  /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
115  ///                         prefix.  If it does, 32-bit register operands stay
116  ///                         32-bit regardless of the operand size.
117  /// @param OpSize           Indicates the operand size of the instruction.
118  ///                         If register size does not match OpSize, then
119  ///                         register sizes keep their size.
120  /// @return               - The operand's type.
121  static OperandType typeFromString(const std::string& s,
122                                    bool hasREX_WPrefix, uint8_t OpSize);
123
124  /// immediateEncodingFromString - Translates an immediate encoding from the
125  ///   string provided in the LLVM tables to an OperandEncoding for use in
126  ///   the operand specifier.
127  ///
128  /// @param s       - See typeFromString().
129  /// @param OpSize  - Indicates whether this is an OpSize16 instruction.
130  ///                  If it is not, then 16-bit immediate operands stay 16-bit.
131  /// @return        - The operand's encoding.
132  static OperandEncoding immediateEncodingFromString(const std::string &s,
133                                                     uint8_t OpSize);
134
135  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
136  ///   handles operands that are in the REG field of the ModR/M byte.
137  static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
138                                                      uint8_t OpSize);
139
140  /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
141  ///   handles operands that are in the REG field of the ModR/M byte.
142  static OperandEncoding roRegisterEncodingFromString(const std::string &s,
143                                                      uint8_t OpSize);
144  static OperandEncoding memoryEncodingFromString(const std::string &s,
145                                                  uint8_t OpSize);
146  static OperandEncoding relocationEncodingFromString(const std::string &s,
147                                                      uint8_t OpSize);
148  static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
149                                                          uint8_t OpSize);
150  static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
151                                                        uint8_t OpSize);
152  static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
153                                                             uint8_t OpSize);
154
155  /// \brief Adjust the encoding type for an operand based on the instruction.
156  void adjustOperandEncoding(OperandEncoding &encoding);
157
158  /// handleOperand - Converts a single operand from the LLVM table format to
159  ///   the emitted table format, handling any duplicate operands it encounters
160  ///   and then one non-duplicate.
161  ///
162  /// @param optional             - Determines whether to assert that the
163  ///                               operand exists.
164  /// @param operandIndex         - The index into the generated operand table.
165  ///                               Incremented by this function one or more
166  ///                               times to reflect possible duplicate
167  ///                               operands).
168  /// @param physicalOperandIndex - The index of the current operand into the
169  ///                               set of non-duplicate ('physical') operands.
170  ///                               Incremented by this function once.
171  /// @param numPhysicalOperands  - The number of non-duplicate operands in the
172  ///                               instructions.
173  /// @param operandMapping       - The operand mapping, which has an entry for
174  ///                               each operand that indicates whether it is a
175  ///                               duplicate, and of what.
176  void handleOperand(bool optional,
177                     unsigned &operandIndex,
178                     unsigned &physicalOperandIndex,
179                     unsigned numPhysicalOperands,
180                     const unsigned *operandMapping,
181                     OperandEncoding (*encodingFromString)
182                       (const std::string&,
183                        uint8_t OpSize));
184
185  /// shouldBeEmitted - Returns the shouldBeEmitted field.  Although filter()
186  ///   filters out many instructions, at various points in decoding we
187  ///   determine that the instruction should not actually be decodable.  In
188  ///   particular, MMX MOV instructions aren't emitted, but they're only
189  ///   identified during operand parsing.
190  ///
191  /// @return - true if at this point we believe the instruction should be
192  ///   emitted; false if not.  This will return false if filter() returns false
193  ///   once emitInstructionSpecifier() has been called.
194  bool shouldBeEmitted() const {
195    return ShouldBeEmitted;
196  }
197
198  /// emitInstructionSpecifier - Loads the instruction specifier for the current
199  ///   instruction into a DisassemblerTables.
200  ///
201  void emitInstructionSpecifier();
202
203  /// emitDecodePath - Populates the proper fields in the decode tables
204  ///   corresponding to the decode paths for this instruction.
205  ///
206  /// \param tables The DisassemblerTables to populate with the decode
207  ///               decode information for the current instruction.
208  void emitDecodePath(DisassemblerTables &tables) const;
209
210  /// Constructor - Initializes a RecognizableInstr with the appropriate fields
211  ///   from a CodeGenInstruction.
212  ///
213  /// \param tables The DisassemblerTables that the specifier will be added to.
214  /// \param insn   The CodeGenInstruction to extract information from.
215  /// \param uid    The unique ID of the current instruction.
216  RecognizableInstr(DisassemblerTables &tables,
217                    const CodeGenInstruction &insn,
218                    InstrUID uid);
219public:
220  /// processInstr - Accepts a CodeGenInstruction and loads decode information
221  ///   for it into a DisassemblerTables if appropriate.
222  ///
223  /// \param tables The DiassemblerTables to be populated with decode
224  ///               information.
225  /// \param insn   The CodeGenInstruction to be used as a source for this
226  ///               information.
227  /// \param uid    The unique ID of the instruction.
228  static void processInstr(DisassemblerTables &tables,
229                           const CodeGenInstruction &insn,
230                           InstrUID uid);
231};
232
233} // namespace X86Disassembler
234
235} // namespace llvm
236
237#endif
238