| de2d8694e25a814696358e95141f4b1aa4d8847e |
20-Sep-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r275480
Bug: http://b/31320715
This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from
aosp/dev.
Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)
Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
pc64-encoding-bookII.s
pc64-encoding-ext.s
pc64-encoding-vmx.s
pc64-encoding.s
pc64-fixups.s
pc64-initial-cfa.s
pc64-localentry.s
t-other-crash.s
sx.s
|
| f3ef5332fa3f4d5ec72c178a2b19dac363a19383 |
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
eprecated-p7.s
pc-llong.s
pc-word.s
pc64-encoding-vmx.s
pc64-encoding.s
pc64-fixup-apply.s
r24686.s
t-other-crash.s
sx.s
|
| 6948897e478cbd66626159776a8017b3c18579b9 |
01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
cbt.s
pc64-encoding-4xx.s
pc64-encoding-6xx.s
pc64-encoding-bookII.s
pc64-encoding-bookIII.s
pc64-encoding-ext.s
pc64-encoding-fp.s
pc64-encoding-p8vector.s
pc64-encoding-vmx.s
pc64-encoding.s
pc64-initial-cfa.s
px.s
t-other-crash.s
sx.s
|
| 0c7f116bb6950ef819323d855415b2f2b0aad987 |
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
pc-reloc.s
pc64-encoding.s
ls-gd-obj.s
ls-ie-obj.s
ls-ld-obj.s
sx.s
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
tm.s
pc64-encoding-bookII.s
pc64-encoding-vmx.s
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
pc-reloc.s
pc64-encoding-ext.s
pc64-encoding-fp.s
pc64-encoding-vmx.s
pc64-encoding.s
pc64-localentry.s
px.s
sx.s
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
comm.s
pc-reloc.s
pc32-ba.s
pc64-abiversion.s
pc64-encoding-4xx.s
pc64-encoding-6xx.s
pc64-encoding-bookII.s
pc64-encoding-bookIII.s
pc64-encoding-e500.s
pc64-encoding-ext.s
pc64-encoding-spe.s
pc64-encoding.s
pc64-fixup-apply.s
pc64-fixups.s
pc64-localentry-error1.s
pc64-localentry-error2.s
pc64-localentry.s
sx.s
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
it.local.cfg
pc64-initial-cfa.s
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
pc64-initial-cfa.s
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
eprecated-p7.s
pc-llong.s
pc-machine.s
pc-nop.s
pc-word.s
pc64-encoding-bookII.s
pc64-encoding-bookIII.s
pc64-encoding-ext.s
pc64-encoding-fp.s
pc64-encoding-vmx.s
pc64-encoding.s
pc64-errors.s
pc64-fixup-apply.s
pc64-fixup-explicit.s
pc64-fixups.s
pc64-initial-cfa.s
pc64-operands.s
pc64-regs.s
sx.s
|
| 136660484d56ac5bb168e0c3a8f6fbc9d986723e |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193548 91177308-0d34-0410-b5e6-96231b3b80d8
ls-ie-obj.s
|
| 61e4743913b68daec52460a8447cbe7e210626e9 |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193547 91177308-0d34-0410-b5e6-96231b3b80d8
ls-ld-obj.s
|
| 82c2703167bcc4132ff6eeff128268d8d13029a1 |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193546 91177308-0d34-0410-b5e6-96231b3b80d8
ls-gd-obj.s
|
| 9637da60835a60f8ccd8289d04c60b2dcd4b9b5a |
26-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros. This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.
N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate. If that behavior is needed,
we can change writeNopData() to behave in the same way.
This fixes PR17352.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426 91177308-0d34-0410-b5e6-96231b3b80d8
pc-nop.s
|
| 11c2b15c0a8282cfdc1c74968ebaba92f1fdae34 |
26-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.
This fixes PR17350.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-fp.s
|
| 3f22cc1df64a6dd6a3ecc5e7e261f15af083f806 |
25-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
MC: Add support for treating $ as a reference to the PC
The binutils assembler supports a mode called DOLLAR_DOT which treats
the dollar sign token as a reference to the current program counter if
the dollar sign doesn't precede a constant or identifier.
This commit adds a new MCAsmInfo flag stating whether or not a given
target supports this interpretation of the dollar sign token; by
default, this flag is not enabled.
Further, enable this flag for PPC. The system assembler for AIX and
binutils both support using the dollar sign in this manner.
This fixes PR17353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191368 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-operands.s
|
| ba7183bc5284a0e4254ad12b78e2ea61e291dd88 |
12-Sep-2013 |
Roman Divacky <rdivacky@freebsd.org> |
Implement asm support for a few PowerPC bookIII that are needed for assembling
FreeBSD kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190618 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-bookIII.s
|
| c0b12dfd0a83081c1ebbb55a89c7a2c1f98f1842 |
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Mark PPC MFTB and DST (and friends) as deprecated
Use the new instruction deprecation feature to mark mftb (now replaced with
mfspr) and dst (along with the other Altivec cache control instructions) as
deprecated when targeting cores supporting at least ISA v2.03.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190605 91177308-0d34-0410-b5e6-96231b3b80d8
eprecated-p7.s
|
| 66b7139b1be1ddce410d97499d5831231c6be267 |
27-Aug-2013 |
Joerg Sonnenberger <joerg@bec.de> |
Given target assembler parsers a chance to handle variant expressions
first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189400 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-errors.s
pc64-fixups.s
|
| 953a78084b85ea88cd2b208153a72df70e27133f |
19-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC fcpsgn instruction
Modern PPC cores support a floating-point copysign instruction, and we can use
this to lower the FCOPYSIGN node (which is created from calls to the libm
copysign function). A couple of extra patterns are necessary because the
operand types of FCOPYSIGN need not agree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188653 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-fp.s
|
| 24ec2e5a72d7fca58f8ae2b3c01501a9927ef04e |
16-Aug-2013 |
Daniel Dunbar <daniel@zuster.org> |
[tests] Cleanup initialization of test suffixes.
- Instead of setting the suffixes in a bunch of places, just set one master
list in the top-level config. We now only modify the suffix list in a few
suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).
- Aside from removing the need for a bunch of lit.local.cfg files, this enables
4 tests that were inadvertently being skipped (one in
Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
XFAILED).
- This commit also fixes a bunch of config files to use config.root instead of
older copy-pasted code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
it.local.cfg
|
| dcef6a7400d51526a04a18e274bd579da262e9ad |
12-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
Fix FileCheck --check-prefix lines.
Various tests had sprung up over the years which had --check-prefix=ABC on the
RUN line, but "CHECK-ABC:" later on. This happened to work before, but was
strictly incorrect. FileCheck is getting stricter soon though.
Patch by Ron Ofir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188173 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixup-explicit.s
pc64-fixups.s
|
| 7a34599db017a5486cf7cd11eb124984acec8286 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Revert r185476 and fix up TLS variant kinds
In the commit message to r185476 I wrote:
>The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
>correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
>This causes some confusion with the asm parser, since VK_PPC_TLSGD
>is output as @tlsgd, which is then read back in as VK_TLSGD.
>
>To avoid this confusion, this patch removes the PowerPC-specific
>modifiers and uses the generic modifiers throughout. (The only
>drawback is that the generic modifiers are printed in upper case
>while the usual convention on PowerPC is to use lower-case modifiers.
>But this is just a cosmetic issue.)
This was unfortunately incorrect, there is is fact another,
serious drawback to using the default VK_TLSLD/VK_TLSGD
variant kinds: using these causes ELFObjectWriter::RelocNeedsGOT
to return true, which in turn causes the ELFObjectWriter to emit
an undefined reference to _GLOBAL_OFFSET_TABLE_.
This is a problem on powerpc64, because it uses the TOC instead
of the GOT, and the linker does not provide _GLOBAL_OFFSET_TABLE_,
so the symbol remains undefined. This means shared libraries
using TLS built with the integrated assembler are currently
broken.
While the whole RelocNeedsGOT / _GLOBAL_OFFSET_TABLE_ situation
probably ought to be properly fixed at some point, for now I'm
simply reverting the r185476 commit. Now this in turn exposes
the breakage of handling @tlsgd/@tlsld in the asm parser that
this check-in was originally intended to fix.
To avoid this regression, I'm also adding a different fix for
this problem: while common code now parses @tlsgd as VK_TLSGD,
a special hack in the asm parser translates this code to the
platform-specific VK_PPC_TLSGD that the back-end now expects.
While this is not really pretty, it's self-contained and
shouldn't hurt anything else for now. One the underlying
problem is fixed, this hack can be reverted again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185945 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| b2713e018e1c99bb9a65d2d2e63dc7e3e2222c57 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support ".machine any"
The PowerPC assembler is supposed to provide a directive .machine
that allows switching the supported CPU instruction set on the fly.
Since we do not yet check CPU feature sets at all and always accept
any available instruction, this is not really useful at this point.
However, it makes sense to accept (and ignore) ".machine any" to
avoid spuriously rejecting existing assembler files that use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185924 91177308-0d34-0410-b5e6-96231b3b80d8
pc-machine.s
|
| ff16df71f50231c79c379a146dc55b4d6867cbd9 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support .llong and fix .word
This adds support for the .llong PowerPC-specifc assembler directive.
In doing so, I notices that .word is currently incorrect: it is
supposed to define a 2-byte data element, not a 4-byte one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185911 91177308-0d34-0410-b5e6-96231b3b80d8
pc-llong.s
pc-word.s
pc64-fixup-apply.s
|
| 19d2b78978905cfde0a0d7190c8480219fb2d1c6 |
08-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support time base instructions
This adds support for the old-style time base instructions;
while new programs are supposed to use mfspr, the mftb instructions
are still supported and in use by existing assembler files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185829 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-bookII.s
|
| 9e5bbeab1f6f79375c24bfab87c28f5f4c5afea1 |
08-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support basic compare mnemonics
This adds support for the basic mnemoics (with the L operand) for the
fixed-point compare instructions. These are defined as aliases for the
already existing CMPW/CMPD patterns, depending on the value of L.
This requires use of InstAlias patterns with immediate literal operands.
To make this work, we need two further changes:
- define a RegisterPrefix, because otherwise literals 0 and 1 would
be parsed as literal register names
- provide a PPCAsmParser::validateTargetOperandClass routine to
recognize immediate literals (like ARM does)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185826 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding.s
|
| 457571ed6977f78ca8d30b993fa7e86e2d7ad8d5 |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some special @got@tprel fixup cases
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.
However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.
The same applies for the @got@dtprel variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| 3d4427347e5d540d22bd135535282761efb6bd6e |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Make test case buildable with GNU as
The ppc64-fixups.s test currently fails to build with GNU as, since it
does not support plain symbols as arguments to li/lis. Rewrite the test
for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead.
Allowing the test case to be built with both LLVM and GNU as makes it
easier to spot unwanted difference in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185694 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| 23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
add 3, 4, symbol@tls
The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant. This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS. This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.
As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-errors.s
pc64-fixups.s
|
| 972befb3f281f0f9ce08d7cf27b4e879327676b0 |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Implement writeNopData
This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.
This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662 91177308-0d34-0410-b5e6-96231b3b80d8
pc-nop.s
|
| 3c99602ca87f604080e367838180c3d63f6931f3 |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add all trap mnemonics
This adds support for all basic and extended variants
of the trap instructions to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
pc64-encoding.s
|
| 5606fcae50951e9d9aef7def18531b5fd017971b |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add asm parser support for CR expressions
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 51f558c9aed3bf74c2e8f3ff3bf365c94637ecdf |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support lmw/stmw in the asm parser
This adds support for the load/store multiple instructions,
currently used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding.s
|
| 33efedc0481c4b0d9866ff526eb1161372b5919f |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.
Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.
To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.
As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
pc64-encoding.s
|
| 44175d9715268bfb7c2cb10ebf14474f4a411464 |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser. The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
pc64-encoding.s
|
| 25b9bbae69befa03cc48d4be73b741eff8e523bc |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] PR16512 - Support TLS call sequences in the asm parser
This patch now adds support for recognizing TLS call sequences in
the asm parser. This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop. That pattern is used for the
asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| 75dd57a8f0407be32551cf695e63a106dd051a27 |
02-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:
1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.
2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).
3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.
4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.
With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-regs.s
|
| 228e0afcfd0d5f167a95c6ddbec2c6a4a90b6d2b |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
.quad target@dtpmod
.quad target@tprel
.quad target@dtprel
Currently exploited by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| 1307d8300f6fe97059998480c42b44faefbc9b99 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
pc64-encoding.s
|
| 3bd2b92267df204c5633329611cc7ae3e1c11834 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185375 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-bookII.s
|
| 222e781d92541017c3a9c5dd40cb52e334cdb86f |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix @got references to local symbols
A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.
Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185353 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixup-explicit.s
|
| 62c1baf8b58a40d37f56a5431214e6514e42970f |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add "wait" instruction
This adds the "wait" instruction and its extended mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185350 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-bookII.s
|
| c0a6b981de8efd2c68125edb94bf9ffb933df727 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support "eieio" instruction
This adds support for the "eieio" instruction to
the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185349 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-bookII.s
|
| 4c1d023de889428e3ea17767b9a7238901c66eff |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some existing instructions to ppc64-encoding-bookII.s
The test case had a couple of FIXMEs where the instruction is in
fact already supported by the back-end. In some other case, while
the generic form of the instruction is not yet supported, a
specialized form is. This adds tests for those already supported
instructions / instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185347 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-bookII.s
|
| af679a22923d2b61e3bfb6721bd562b99546bfad |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add variants of "sync" instruction
This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185344 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-bookII.s
|
| 8950dd127ad4cccd9dadf616b5057cf130f24ade |
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Accept 17-bit signed immediates for addis
The assembler currently strictly verifies that immediates for
s16imm operands are in range (-32768 ... 32767). This matches
the behaviour of the GNU assembler, with one exception: gas
allows, as a special case, operands in an extended range
(-65536 .. 65535) for the addis instruction only (and its
extended mnemonic lis).
The main reason for this seems to be to allow using unsigned
16-bit operands for lis, e.g. like lis %r1, 0xfedc.
Since this has been supported by gas for a long time, and
assembler source code seen "in the wild" actually exploits
this feature, this patch adds equivalent support to LLVM
for compatibility reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184946 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-errors.s
pc64-operands.s
|
| 0b8594268feb1c804370541c7853e658caee0ae5 |
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic
operands. However, for u16imm operands, we only support actual
immediate integers. This causes the assembler to reject code like
ori %r5, %r5, symbol@l
This patch changes the u16imm operand definition to likewise
accept symbolic operands. In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| 5de735a962a255676cf3a9bc255579d465670633 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @got modifier
Add VK_... values and relocation types necessary to support
the @got family of modifiers. Used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184860 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| 1bc147c0910bb02398730c79e0d0310ffbbd2868 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add extended rotate/shift mnemonics
This adds all missing extended rotate/shift mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184834 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 816c06f7fa73e8150e260a11d897be2f52d4f2b8 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add rldcr/rldic instructions
This adds pattern for the rldcr and rldic instructions (the last instruction
from the rotate/shift family that were missing). They are currently used
only by the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184833 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding.s
|
| 9c52f81e1787dc9666e510f5b7a0ea75b697cd0b |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add extended subtract mnemonics
This adds support for the extended subtract mnemonics to the asm parser:
subi
subis
subic
subic.
sub
sub.
subc
subc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184832 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 96fb3a25cb0007f06d22d28c0b9c3503798324f6 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support some miscellaneous mnemonics in the asm parser
This adds support for the following extended mnemonics:
xnop
mr.
not
not.
la
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184767 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 329d41319996d943e97180307df7e1600198d356 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some FIXMEs
A bunch of extendend mnemomics ought to support '.' forms.
Add FIXMEs to the test case for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184757 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 2e8bd8950345b0857130dd0f4068222a79c103f2 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
For these, I've added new PPC::Predicate codes corresponding
to the BO values for predicted branch forms, and updated insn
printing to print them correctly. I've also added new aliases
for the asm parser matching the new forms.
- bt/bf
I've added new aliases matching to gBC etc.
- bd(n)z variants
I've added new instruction patterns for the predicted forms.
In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 48473a8de50d6047432a3619e4781788ba004c93 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add t/f branch mnemonics to asm parser
This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184725 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| e5a30f0ca22cc1ba97478e9fadcdef02d341004e |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support generic conditional branches in asm parser
This adds instruction patterns to cover the generic forms of
the conditional branch instructions. This allows the assembler
to support the generic mnemonics.
The compiler will still generate the various specific forms
of the instruction that were already supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184722 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding.s
|
| 9679c47a07386cbf3547a0927609c7ee080b2aab |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions. This patch adds support for the absolute
variants of all branches that are currently otherwise supported.
This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.
While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
pc64-encoding.s
pc64-fixups.s
pc64-operands.s
|
| 9068d5310cfafdd201f77b0434dc7eebb7f51a45 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support bd(n)zl and bd(n)zlrl
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184720 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 813942a0cf8e0605002c5fa364372a8a61634cc4 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support b(cond)l in the asm parser
This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184719 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 7e66f5c1b4a166d823e0452d1a1bc0f822d04201 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support blrl and variants in the asm parser
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184718 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 84569698f01bcb49afe5b6140bf0d61cf4f3cf5a |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support R_PPC_REL16 family of relocations
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:
li 1, base-.
This patch adds support for those relocation types in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184552 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| cab0a1933875935c717136d251e2af9749533ba8 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support various tls-related modifiers
The current code base only supports the minimum set of tls-related
relocations and @modifiers that are necessary to support compiler-
generated code. This patch extends this to the full set defined
in the ABI (and supported by the GNU assembler) for the benefit
of the assembler parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184551 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| f7c1ee79fe90353fcd3f545f9d45a01a837bbf4b |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @higher et.al. modifiers
This adds support for the @higher, @highera, @highest, and @highesta
modifers, including some missing relocation types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184550 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixup-apply.s
pc64-fixups.s
|
| f8f87dcfceadd1b842d130303a7091ad7d7d67d0 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @toc@h modifier
This adds the relocation type and other necessary infrastructure
to use the @toc@h modifier in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184549 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| d2849572463da994c685b3bd7a60d5a7566c01e3 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @h modifier
This adds necessary infrastructure to support the @h modifier.
Note that all required relocation types were already present
(and unused).
This patch provides support for using @h in the assembler;
it would also be possible to now use this feature in code
generated by the compiler, but this is not done yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184548 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixup-apply.s
pc64-fixups.s
|
| 151ad37fed2685f020bbed5b342ad7c0c35616bd |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[MC] Support @ variants with directional labels
The assembler parser common code supports recognizing symbol variants
using the @ modifer. On PowerPC, it should also be possible to use
(some of) those modifiers with directional labels, like "1f@l".
This patch adds support for accepting symbol variants on directional
labels as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184437 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixup-apply.s
|
| 027e94479c9e69eb3c3c5536fa9990d0b96e9510 |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Optimize @ha/@l constructs
This patch adds support for having the assembler optimize fixups
to constructs like "symbol@ha" or "symbol@l" if "symbol" can be
resolved at assembler time.
This optimization is already present in the PPCMCExpr.cpp code
for handling PPC_HA16/PPC_LO16 target expressions. However,
those target expression were used only on Darwin targets.
This patch changes target expression code so that they are
usable also with the GNU assembler (using the @ha / @l syntax
instead of the ha16() / lo16() syntax), and changes the
MCInst lowering code to generate those target expressions
where appropriate.
It also changes the asm parser to generate HA16/LO16 target
expressions when parsing assembler source that uses the
@ha / @l modifiers. The effect is that now the above-
mentioned optimization automatically becomes available
for those situations too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184436 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixup-apply.s
|
| 0db5379fe643cbe738b4831e337251819cc5dc5d |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| c1f4a4b2640dfc871bacacef53a95f1c96a9fe48 |
12-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[MC/DWARF] Support .debug_frame / .debug_line code alignment factors
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.
In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4. However, current MC code hard-codes a code
alignment factor of 1.
This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.
This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc. Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available. However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it. If it turns out to be needed again at a later time, it
could be re-added with an updated interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183834 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-initial-cfa.s
|
| e48e8c7a6069374daee4c9be1e17b8ed31527f5e |
12-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use assembler source in MC tests
A couple of old test cases in test/MC/PowerPC were still using
LLVM IR. Now that we have a working assembler, we can move
them to assembler tests instead:
ppc64-initial-cfa.ll
ppc64-relocs-01.ll
ppc64-tls-relocs-01.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183829 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-initial-cfa.ll
pc64-initial-cfa.s
pc64-relocs-01.ll
pc64-relocs-01.s
pc64-tls-relocs-01.ll
pc64-tls-relocs-01.s
|
| 278916500a2d7c735e3ed6b0f57cd757815b9867 |
10-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support extended sc mnemonic
A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler. This patch adds a corresponding alias.
Problem reported by Joerg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183687 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding.s
|
| 7c6f90d486911076da01ec0f37af4760fdd7041f |
10-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support branch mnemonics with implied CR0
The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified. This patch
adds extra variants of the mnemonics to this effect.
Problem reported by Joerg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183686 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 7486d92a6c949a193bb75c0ffa0170eeb2fabb80 |
30-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change how we iterate over relocations on ELF.
For COFF and MachO, sections semantically have relocations that apply to them.
That is not the case on ELF.
In relocatable objects (.o), a section with relocations in ELF has offsets to
another section where the relocations should be applied.
In dynamic objects and executables, relocations don't have an offset, they have
a virtual address. The section sh_info may or may not point to another section,
but that is not actually used for resolving the relocations.
This patch exposes that in the ObjectFile API. It has the following advantages:
* Most (all?) clients can handle this more efficiently. They will normally walk
all relocations, so doing an effort to iterate in a particular order doesn't
save time.
* llvm-readobj now prints relocations in the same way the native readelf does.
* probably most important, relocations that don't point to any section are now
visible. This is the case of relocations in the rela.dyn section. See the
updated relocation-executable.test for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-initial-cfa.ll
pc64-relocs-01.ll
pc64-tls-relocs-01.ll
|
| e152eac63efa836cbb109d79e4307516fa16f1a6 |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Merge/rename PPC fixup types
Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly
the same everywhere, it no longer makes sense to have two fixup types.
This patch merges them both into a single type fixup_ppc_half16,
and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency.
(The half16 and half16ds names are taken from the description of
relocation types in the PowerPC ABI.)
No change in code generation expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| c299ad32c8e59ceea05ede15e1c59ac787d17feb |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixup-apply.s
pc64-fixups.s
|
| 9122396a4dea52cf917062782fc2f39c7dc698bb |
15-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove need for adjustFixupOffst hack
Now that applyFixup understands differently-sized fixups, we can define
fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte
fixups, applied at an offset of 2 relative to the start of the
instruction text.
This has the benefit that if we actually need to generate a real
relocation record, its address will come out correctly automatically,
without having to fiddle with the offset in adjustFixupOffset.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| e66ef733188f06f24baa8fe496abd9eab442b3b0 |
15-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add test case for r181891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181892 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixup-apply.s
|
| 5bbdb190412a55436b808cfa59820b1e6cf08db0 |
14-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Implement the PowerPC system call (sc) instruction.
Instruction added at request of Roman Divacky. Tested via asm-parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding.s
|
| 146f336272f442e8342ef9bbfa5f5937c4bb8d65 |
08-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add ELF relocation tests
This patch extends test/MC/PowerPC/ppc64-fixups.s to not only check for
the correct fixup type in the --show-encoding output, but also runs the
generated object file through llvm-readobj -r and verifies that the
correct ELF relocation records were generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181453 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| a7e5e6b959bfd2b7982e116a4fd6955b35534b4c |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Parse platform-specifc variant kinds in AsmParser
This patch adds support for PowerPC platform-specific variant
kinds in MCSymbolRefExpr::getVariantKindForName, and also
adds a test case to verify they are translated to the appropriate
fixup type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181053 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-fixups.s
|
| 8e4ba8f7b19615907e5874b3aa661d52c21fff74 |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some Book II instructions to AsmParser
This patch adds a couple of Book II instructions (isync, icbi) to the
PowerPC assembler parser. These are needed when bootstrapping clang
with the integrated assembler forced on, because they are used in
inline asm statements in the code base.
The test case adds the full list of Book II storage control instructions,
including associated extended mnemonics. Again, those that are not yet
supported as marked as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-bookII.s
|
| 16adfdb2e666f46e058b603a8a7aa75758819fd5 |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support extended mnemonics in AsmParser
This patch adds infrastructure to support extended mnemonics in the
PowerPC assembler parser. It adds support specifically for those
extended mnemonics that LLVM will itself generate.
The test case lists *all* extended mnemonics according to the
PowerPC ISA v2.06 Book I, but marks those not yet supported
as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-ext.s
|
| 5e220753ff81ac5cbee874e7c00c76c7fbe0d20a |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.
The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux. The supported syntax is
intended to be compatible with the GNU assembler.
The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.
Instruction operands will be checked for validity and errors
generated. (Error handling in general could still be improved.)
The patch adds a number of test cases to verify instruction
and operand encodings. The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector.
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.
A number of follow-on check-ins will add extra features. When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-encoding-fp.s
pc64-encoding-vmx.s
pc64-encoding.s
pc64-errors.s
pc64-operands.s
|
| f89da7210b09a0a0f7c9ee216cd54dca03c6b64a |
12-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Replace coff-/elf-dump with llvm-readobj
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-initial-cfa.ll
pc64-relocs-01.ll
pc64-tls-relocs-01.ll
|
| a1db5de9e70dd8ffda57b1a4373915ea866b6f1d |
09-Jan-2013 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: EH adjustments
This patch adjust the r171506 to make all DWARF enconding pc-relative
for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT
(since the eh_frame will not generate PIC-relative relocation) and also
adds the emission of stubs created by the TTypeEncoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171979 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-initial-cfa.ll
|
| 7b449889e7886b263718b5103538970f287bc37e |
04-Jan-2013 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Fix eh_frame relocation for PIC
This patch fixes the PPC eh_frame definitions for the personality and
frame unwinding for PIC objects. It makes PIC build correctly creates
relative relocations in the '.rela.eh_frame' segments and thus avoiding
a text relocation that generates a DT_TEXTREL segments in link phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171506 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-initial-cfa.ll
|
| 781dfbd482c5177215ae7a43c9483e641eeb0d47 |
28-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix initial frame state on powerpc64.
The createPPCMCAsmInfo routine used PPC::R1 as the initial frame
pointer register, but on PPC64 the 32-bit R1 register does not
have a corresponding DWARF number, causing invalid CIE initial
frame state to be emitted. Fix by using PPC::X1 instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168799 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-initial-cfa.ll
|
| 527388dea5b4220f463a7cef6b1012770d1a80a5 |
15-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch is in preparation for adding medium code model support to the
PPC64 target. The five tests modified herein test code generation that is
sensitive to the code model selected. So I've added -code-model=small to
the RUN commands for each.
Since small code model is the default, this has no effect for now; but this
prepares us for eventually changing the default to medium code model for PPC64.
Test changes verified with small and medium code model as default on
powerpc64-unknown-linux-gnu. All tests continue to pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167999 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-relocs-01.ll
|
| 51abc9877e229bddf258d24386ab8d394e93ac33 |
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Add test case to verify correct relocs being generated for
TLS symbols on PowerPC using the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167875 91177308-0d34-0410-b5e6-96231b3b80d8
pc64-tls-relocs-01.ll
|
| aa71428378c1cb491ca60041d8ba7aa110bc963d |
25-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
Initial TOC support for PowerPC64 object creation
This patch adds initial PPC64 TOC MC object creation using the small mcmodel
(a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC,
R_PPC64_TOC16, and R_PPC64_TOC16DS).
The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter'
is meant to avoid the creation of an unreferenced ".TOC." symbol (used in
the .odp creation) as well to set the R_PPC64_TOC relocation target as the
temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should
not point to any symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166677 91177308-0d34-0410-b5e6-96231b3b80d8
it.local.cfg
pc64-relocs-01.ll
|