Lines Matching refs:Reg
61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
98 // Create a new GroupNode for Reg. Reg's existing GroupNode must
103 GroupNodeIndices[Reg] = idx;
107 bool AggressiveAntiDepState::IsLive(unsigned Reg)
111 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
161 unsigned Reg = *Alias; ++Alias) {
162 State->UnionGroups(Reg, 0);
163 KillIndices[Reg] = BB->size();
164 DefIndices[Reg] = ~0u;
177 unsigned Reg = *Alias; ++Alias) {
178 State->UnionGroups(Reg, 0);
179 KillIndices[Reg] = BB->size();
180 DefIndices[Reg] = ~0u;
190 unsigned Reg = *I;
191 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
192 for (const unsigned *Alias = TRI->getOverlaps(Reg);
220 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
221 // If Reg is current live, then mark that it can't be renamed as
227 if (State->IsLive(Reg)) {
228 DEBUG(if (State->GetGroup(Reg) != 0)
229 dbgs() << " " << TRI->getName(Reg) << "=g" <<
230 State->GetGroup(Reg) << "->g0(region live-out)");
231 State->UnionGroups(Reg, 0);
232 } else if ((DefIndices[Reg] < InsertPosIndex)
233 && (DefIndices[Reg] >= Count)) {
234 DefIndices[Reg] = Count;
246 unsigned Reg = MO.getReg();
247 if (Reg == 0)
252 Op = MI->findRegisterUseOperand(Reg, true);
254 Op = MI->findRegisterDefOperand(Reg);
266 const unsigned Reg = MO.getReg();
267 PassthruRegs.insert(Reg);
268 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
283 unsigned Reg = P->getReg();
284 if (RegSet.count(Reg) == 0) {
286 RegSet.insert(Reg);
317 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
326 if (!State->IsLive(Reg)) {
327 KillIndices[Reg] = KillIdx;
328 DefIndices[Reg] = ~0u;
329 RegRefs.erase(Reg);
330 State->LeaveGroup(Reg);
332 dbgs() << header << TRI->getName(Reg); header = NULL; });
333 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
336 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
345 dbgs() << header << TRI->getName(Reg); header = NULL; });
369 unsigned Reg = MO.getReg();
370 if (Reg == 0) continue;
372 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
379 unsigned Reg = MO.getReg();
380 if (Reg == 0) continue;
382 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
389 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
390 State->UnionGroups(Reg, 0);
394 // partially defined here, so group those aliases with Reg.
395 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
398 State->UnionGroups(Reg, AliasReg);
399 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
409 RegRefs.insert(std::make_pair(Reg, RR));
419 unsigned Reg = MO.getReg();
420 if (Reg == 0) continue;
422 if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
425 // Update def for Reg and aliases.
426 for (const unsigned *Alias = TRI->getOverlaps(Reg);
463 unsigned Reg = MO.getReg();
464 if (Reg == 0) continue;
466 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
467 State->GetGroup(Reg));
472 HandleLastUse(Reg, Count, "(last-use)");
475 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
476 State->UnionGroups(Reg, 0);
484 RegRefs.insert(std::make_pair(Reg, RR));
498 unsigned Reg = MO.getReg();
499 if (Reg == 0) continue;
502 DEBUG(dbgs() << "=" << TRI->getName(Reg));
503 State->UnionGroups(FirstReg, Reg);
505 DEBUG(dbgs() << " " << TRI->getName(Reg));
506 FirstReg = Reg;
514 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
518 // Check all references that need rewriting for Reg. For each, use
525 Range = State->GetRegRefs().equal_range(Reg);
572 unsigned Reg = Regs[i];
573 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
574 SuperReg = Reg;
576 // If Reg has any references, then collect possible rename regs
577 if (RegRefs.count(Reg) > 0) {
578 DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
580 BitVector BV = GetRenameRegisters(Reg);
581 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
592 unsigned Reg = Regs[i];
593 if (Reg == SuperReg) continue;
594 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
653 unsigned Reg = Regs[i];
655 if (Reg == SuperReg) {
658 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
665 // Check if Reg can be renamed to NewReg.
666 BitVector BV = RenameRegisterMap[Reg];
673 // Regs's kill, it's safe to replace Reg with NewReg. We
676 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
685 (KillIndices[Reg] > DefIndices[AliasReg])) {
695 // Record that 'Reg' can be renamed to 'NewReg'.
696 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
767 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
768 if (!State->IsLive(Reg))
769 DEBUG(dbgs() << " " << TRI->getName(Reg));