Lines Matching defs:MO
67 /// Note that operands may be added, so the MO reference is no longer valid.
68 static void substitutePhysReg(MachineOperand &MO, unsigned Reg,
70 if (MO.getSubReg()) {
71 MO.substPhysReg(Reg, TRI);
77 MachineInstr &MI = *MO.getParent();
78 if (MO.isUse() && !MO.isUndef() &&
79 (MO.isKill() || MI.isRegTiedToDefOperand(&MO-&MI.getOperand(0))))
82 MO.setReg(Reg);
547 MachineOperand &MO = MI.getOperand(i);
548 if (!MO.isReg() || !MO.isUse() || !MO.isKill() || MO.isUndef())
550 unsigned Reg = MO.getReg();
556 if (KillOps[Reg] == &MO) {
562 assert(KillOps[*SR] == &MO && "bad subreg kill flags");
589 MachineOperand &MO = DefMI->getOperand(i);
590 if (!MO.isReg() || !MO.isDef() || !MO.isKill() || MO.isUndef())
592 if (MO.getReg() == Reg)
593 DefOp = &MO;
594 else if (!MO.isDead())
606 MachineOperand &MO = NMI->getOperand(j);
607 if (!MO.isReg() || MO.getReg() == 0 ||
608 (MO.getReg() != Reg && !TRI->isSubRegister(Reg, MO.getReg())))
610 if (MO.isUse())
633 MachineOperand &MO = MI.getOperand(i);
634 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
636 unsigned Reg = MO.getReg();
643 if (MO.isKill()) {
645 KillOps[Reg] = &MO;
648 KillOps[*SR] = &MO;
654 const MachineOperand &MO = MI.getOperand(i);
655 if (!MO.isReg() || !MO.getReg() || !MO.isDef())
657 unsigned Reg = MO.getReg();
689 MachineOperand &MO = NewMI->getOperand(i);
690 if (!MO.isReg() || MO.getReg() == 0)
692 unsigned VirtReg = MO.getReg();
695 assert(MO.isUse());
698 substitutePhysReg(MO, Phys, *TRI);
1003 MachineOperand &MO = MI.getOperand(i);
1004 if (!MO.isReg() || MO.getReg() == 0)
1006 unsigned Reg = MO.getReg();
1043 MachineOperand &MO = PrevMI->getOperand(i);
1044 if (!MO.isReg() || MO.getReg() == 0)
1046 unsigned Reg = MO.getReg();
1047 if (MO.isDef()) {
1053 if (MO.isKill() && AllocatableRegs[Reg])
1079 MachineOperand &MO = MI->getOperand(i);
1080 if (MO.isReg() && MO.getReg() == VirtReg)
1081 substitutePhysReg(MO, PhysReg, TRI);
1424 MachineOperand &MO = MI.getOperand(i);
1425 if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse())
1427 unsigned VirtReg = MO.getReg();
1428 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
1675 MachineOperand &MO = MI.getOperand(i);
1676 if (!MO.isReg() || !MO.getReg())
1678 if (MO.isDef() && !MO.isDead())
1680 if (MO.isUse() && MO.isKill())
1718 MachineOperand &MO = LastUDMI->getOperand(i);
1719 if (!MO.isReg() || MO.getReg() != Reg)
1721 if (!LastUD || (LastUD->isUse() && MO.isDef()))
1722 LastUD = &MO;
1928 MachineOperand &MO = MI.getOperand(i);
1929 if (!MO.isReg() || MO.getReg() == 0)
1932 unsigned VirtReg = MO.getReg();
1942 if (MO.isImplicit())
1956 if (MO.isDef() && MO.getSubReg() && MI.readsVirtualRegister(VirtReg) &&
2497 MachineOperand &MO = MI.getOperand(i);
2498 if (!(MO.isReg() && MO.getReg() && MO.isDef()))
2501 unsigned VirtReg = MO.getReg();
2514 if (MO.isDead() && !KillRegs.empty()) {
2546 unsigned SubIdx = MO.getSubReg();
2588 if (!MO.isDead() && SpilledMIRegs.insert(VirtReg)) {