| /external/vixl/tools/test_generator/ |
| H A D | data_types.py | 521 class FPSCR(U32): class in inherits:U32
528 __ Vmsr(FPSCR, fpsr_bits);
537 __ Vmrs(RegisterOrAPSR_nzcv(fpsr_bits.GetCode()), FPSCR);
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| /external/vixl/test/aarch32/ |
| H A D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc | 1443 __ Vmsr(FPSCR, fpsr_bits);
1454 __ Vmrs(RegisterOrAPSR_nzcv(fpsr_bits.GetCode()), FPSCR); local
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| H A D | test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc | 1443 __ Vmsr(FPSCR, fpsr_bits);
1454 __ Vmrs(RegisterOrAPSR_nzcv(fpsr_bits.GetCode()), FPSCR); local
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| H A D | test-assembler-aarch32.cc | 141 __ Vmsr(FPSCR, r0); \
2818 __ Vmrs(RegisterOrAPSR_nzcv(r0.GetCode()), FPSCR); local
2821 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); local
2824 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); local
2849 __ Vmrs(RegisterOrAPSR_nzcv(r0.GetCode()), FPSCR); local
2852 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); local
2855 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); local
2880 __ Vmrs(RegisterOrAPSR_nzcv(r0.GetCode()), FPSCR); local
2883 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); local
2886 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); local
2911 __ Vmrs(RegisterOrAPSR_nzcv(r0.GetCode()), FPSCR); local
2914 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); local
2917 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); local
2939 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); local
2943 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); local
2946 __ Vmrs(RegisterOrAPSR_nzcv(pc.GetCode()), FPSCR); local
[all...] |
| /external/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.cc | 503 Vmrs(RegisterOrAPSR_nzcv(tmp.GetCode()), FPSCR); local
599 Vmsr(FPSCR, tmp);
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| /external/valgrind/VEX/priv/ |
| H A D | host_arm_defs.h | 859 according to the FPSCR.RM. For ARM >= V8 hosts only. */
874 /* Move a 32-bit value to/from the FPSCR (FMXR, FMRX) */
878 } FPSCR; member in union:__anon28310::__anon28311
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 3329 // The rounding mode is in bits 23:22 of the FPSCR.
3331 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3334 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, local
3337 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4587 // The rounding mode is in bits 23:22 of the FPSCR.
4589 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4592 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, local
4595 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
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